diff options
author | Alex Waterman <alexw@nvidia.com> | 2018-02-28 12:19:19 -0500 |
---|---|---|
committer | Srikar Srimath Tirumala <srikars@nvidia.com> | 2018-02-28 16:49:22 -0500 |
commit | 5a35a95654d561fce09a3b9abf6b82bb7a29d74b (patch) | |
tree | 119a07134188d8e06c29a570dd8c6b143f39c9e1 /drivers/gpu/nvgpu/gp10b | |
parent | 3fdd8e38b280123fd13bcc4f3fd8928c15e94db6 (diff) |
Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"
Also revert other changes related to IO coherence. This may be the
culprit in a recent dev-kernel lockdown.
Bug 2070609
Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 28 |
2 files changed, 14 insertions, 20 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 1436a260..c82fb1cc 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <nvgpu/dma.h> | 25 | #include <nvgpu/dma.h> |
26 | #include <nvgpu/bug.h> | 26 | #include <nvgpu/bug.h> |
27 | #include <nvgpu/log2.h> | 27 | #include <nvgpu/log2.h> |
28 | #include <nvgpu/enabled.h> | ||
29 | 28 | ||
30 | #include "fifo_gp10b.h" | 29 | #include "fifo_gp10b.h" |
31 | 30 | ||
@@ -79,9 +78,8 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) | |||
79 | nvgpu_mem_wr32(g, &c->inst_block, | 78 | nvgpu_mem_wr32(g, &c->inst_block, |
80 | ram_in_ramfc_w() + ram_fc_userd_w(), | 79 | ram_in_ramfc_w() + ram_fc_userd_w(), |
81 | nvgpu_aperture_mask(g, &g->fifo.userd, | 80 | nvgpu_aperture_mask(g, &g->fifo.userd, |
82 | pbdma_userd_target_sys_mem_ncoh_f(), | 81 | pbdma_userd_target_sys_mem_ncoh_f(), |
83 | pbdma_userd_target_sys_mem_coh_f(), | 82 | pbdma_userd_target_vid_mem_f()) | |
84 | pbdma_userd_target_vid_mem_f()) | | ||
85 | pbdma_userd_addr_f(addr_lo)); | 83 | pbdma_userd_addr_f(addr_lo)); |
86 | 84 | ||
87 | nvgpu_mem_wr32(g, &c->inst_block, | 85 | nvgpu_mem_wr32(g, &c->inst_block, |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 7ff5f6a6..0439dda9 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -124,9 +124,8 @@ int gp10b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
124 | 124 | ||
125 | gk20a_writel(g, bus_bar2_block_r(), | 125 | gk20a_writel(g, bus_bar2_block_r(), |
126 | nvgpu_aperture_mask(g, inst_block, | 126 | nvgpu_aperture_mask(g, inst_block, |
127 | bus_bar2_block_target_sys_mem_ncoh_f(), | 127 | bus_bar2_block_target_sys_mem_ncoh_f(), |
128 | bus_bar2_block_target_sys_mem_coh_f(), | 128 | bus_bar2_block_target_vid_mem_f()) | |
129 | bus_bar2_block_target_vid_mem_f()) | | ||
130 | bus_bar2_block_mode_virtual_f() | | 129 | bus_bar2_block_mode_virtual_f() | |
131 | bus_bar2_block_ptr_f(inst_pa)); | 130 | bus_bar2_block_ptr_f(inst_pa)); |
132 | 131 | ||
@@ -149,9 +148,8 @@ static void update_gmmu_pde3_locked(struct vm_gk20a *vm, | |||
149 | phys_addr >>= gmmu_new_pde_address_shift_v(); | 148 | phys_addr >>= gmmu_new_pde_address_shift_v(); |
150 | 149 | ||
151 | pde_v[0] |= nvgpu_aperture_mask(g, pd->mem, | 150 | pde_v[0] |= nvgpu_aperture_mask(g, pd->mem, |
152 | gmmu_new_pde_aperture_sys_mem_ncoh_f(), | 151 | gmmu_new_pde_aperture_sys_mem_ncoh_f(), |
153 | gmmu_new_pde_aperture_sys_mem_coh_f(), | 152 | gmmu_new_pde_aperture_video_memory_f()); |
154 | gmmu_new_pde_aperture_video_memory_f()); | ||
155 | pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(phys_addr)); | 153 | pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(phys_addr)); |
156 | pde_v[0] |= gmmu_new_pde_vol_true_f(); | 154 | pde_v[0] |= gmmu_new_pde_vol_true_f(); |
157 | pde_v[1] |= phys_addr >> 24; | 155 | pde_v[1] |= phys_addr >> 24; |
@@ -196,7 +194,6 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm, | |||
196 | gmmu_new_dual_pde_address_small_sys_f(small_addr); | 194 | gmmu_new_dual_pde_address_small_sys_f(small_addr); |
197 | pde_v[2] |= nvgpu_aperture_mask(g, pd->mem, | 195 | pde_v[2] |= nvgpu_aperture_mask(g, pd->mem, |
198 | gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(), | 196 | gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(), |
199 | gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(), | ||
200 | gmmu_new_dual_pde_aperture_small_video_memory_f()); | 197 | gmmu_new_dual_pde_aperture_small_video_memory_f()); |
201 | pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); | 198 | pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); |
202 | pde_v[3] |= small_addr >> 24; | 199 | pde_v[3] |= small_addr >> 24; |
@@ -207,7 +204,6 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm, | |||
207 | pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); | 204 | pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); |
208 | pde_v[0] |= nvgpu_aperture_mask(g, pd->mem, | 205 | pde_v[0] |= nvgpu_aperture_mask(g, pd->mem, |
209 | gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(), | 206 | gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(), |
210 | gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(), | ||
211 | gmmu_new_dual_pde_aperture_big_video_memory_f()); | 207 | gmmu_new_dual_pde_aperture_big_video_memory_f()); |
212 | pde_v[1] |= big_addr >> 28; | 208 | pde_v[1] |= big_addr >> 28; |
213 | } | 209 | } |
@@ -244,10 +240,11 @@ static void __update_pte(struct vm_gk20a *vm, | |||
244 | gmmu_new_pte_address_sys_f(phys_shifted) : | 240 | gmmu_new_pte_address_sys_f(phys_shifted) : |
245 | gmmu_new_pte_address_vid_f(phys_shifted); | 241 | gmmu_new_pte_address_vid_f(phys_shifted); |
246 | u32 pte_tgt = __nvgpu_aperture_mask(g, | 242 | u32 pte_tgt = __nvgpu_aperture_mask(g, |
247 | attrs->aperture, | 243 | attrs->aperture, |
248 | gmmu_new_pte_aperture_sys_mem_ncoh_f(), | 244 | attrs->coherent ? |
249 | gmmu_new_pte_aperture_sys_mem_coh_f(), | 245 | gmmu_new_pte_aperture_sys_mem_coh_f() : |
250 | gmmu_new_pte_aperture_video_memory_f()); | 246 | gmmu_new_pte_aperture_sys_mem_ncoh_f(), |
247 | gmmu_new_pte_aperture_video_memory_f()); | ||
251 | 248 | ||
252 | pte_w[0] = pte_valid | pte_addr | pte_tgt; | 249 | pte_w[0] = pte_valid | pte_addr | pte_tgt; |
253 | 250 | ||
@@ -309,7 +306,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, | |||
309 | page_size >> 10, | 306 | page_size >> 10, |
310 | nvgpu_gmmu_perm_str(attrs->rw_flag), | 307 | nvgpu_gmmu_perm_str(attrs->rw_flag), |
311 | attrs->kind_v, | 308 | attrs->kind_v, |
312 | nvgpu_aperture_str(g, attrs->aperture), | 309 | nvgpu_aperture_str(attrs->aperture), |
313 | attrs->cacheable ? 'C' : '-', | 310 | attrs->cacheable ? 'C' : '-', |
314 | attrs->sparse ? 'S' : '-', | 311 | attrs->sparse ? 'S' : '-', |
315 | attrs->priv ? 'P' : '-', | 312 | attrs->priv ? 'P' : '-', |
@@ -431,9 +428,8 @@ void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | |||
431 | 428 | ||
432 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), | 429 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), |
433 | nvgpu_aperture_mask(g, vm->pdb.mem, | 430 | nvgpu_aperture_mask(g, vm->pdb.mem, |
434 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), | 431 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), |
435 | ram_in_page_dir_base_target_sys_mem_coh_f(), | 432 | ram_in_page_dir_base_target_vid_mem_f()) | |
436 | ram_in_page_dir_base_target_vid_mem_f()) | | ||
437 | ram_in_page_dir_base_vol_true_f() | | 433 | ram_in_page_dir_base_vol_true_f() | |
438 | ram_in_big_page_size_64kb_f() | | 434 | ram_in_big_page_size_64kb_f() | |
439 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | | 435 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | |