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authorSunny He <suhe@nvidia.com>2017-08-17 19:11:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit4b5b67d6d83430d8d670660b1dfc9cf024d60d88 (patch)
tree541a421438fe849ee4b1ab9e6bdfa9e8b6ee4485 /drivers/gpu/nvgpu/gp10b
parent82ba1277f3da7379ed6b8288c04bb91db008549c (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ie37638f442fd68aca8a7ade5f297118447bdc91e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542989 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c136
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h86
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c129
3 files changed, 253 insertions, 98 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 05fbeb21..74af9817 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -41,7 +41,7 @@
41 41
42#define NVGPU_GFXP_WFI_TIMEOUT_US 100LL 42#define NVGPU_GFXP_WFI_TIMEOUT_US 100LL
43 43
44static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) 44bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
45{ 45{
46 bool valid = false; 46 bool valid = false;
47 47
@@ -67,7 +67,7 @@ static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
67 return valid; 67 return valid;
68} 68}
69 69
70static bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num) 70bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
71{ 71{
72 if (class_num == PASCAL_A || class_num == MAXWELL_B) 72 if (class_num == PASCAL_A || class_num == MAXWELL_B)
73 return true; 73 return true;
@@ -75,7 +75,7 @@ static bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
75 return false; 75 return false;
76} 76}
77 77
78static bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num) 78bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num)
79{ 79{
80 if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) 80 if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B)
81 return true; 81 return true;
@@ -119,7 +119,7 @@ static void gr_gp10b_sm_lrf_ecc_overcount_war(int single_err,
119 *count_to_adjust = 0; 119 *count_to_adjust = 0;
120} 120}
121 121
122static int gr_gp10b_handle_sm_exception(struct gk20a *g, 122int gr_gp10b_handle_sm_exception(struct gk20a *g,
123 u32 gpc, u32 tpc, u32 sm, 123 u32 gpc, u32 tpc, u32 sm,
124 bool *post_event, struct channel_gk20a *fault_ch, 124 bool *post_event, struct channel_gk20a *fault_ch,
125 u32 *hww_global_esr) 125 u32 *hww_global_esr)
@@ -244,7 +244,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g,
244 return ret; 244 return ret;
245} 245}
246 246
247static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, 247int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
248 bool *post_event) 248 bool *post_event)
249{ 249{
250 int ret = 0; 250 int ret = 0;
@@ -380,7 +380,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
380 return ret; 380 return ret;
381} 381}
382 382
383static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, 383int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
384 struct channel_gk20a *c, bool patch) 384 struct channel_gk20a *c, bool patch)
385{ 385{
386 struct gr_gk20a *gr = &g->gr; 386 struct gr_gk20a *gr = &g->gr;
@@ -481,7 +481,7 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
481 return 0; 481 return 0;
482} 482}
483 483
484static void gr_gp10b_commit_global_pagepool(struct gk20a *g, 484void gr_gp10b_commit_global_pagepool(struct gk20a *g,
485 struct channel_ctx_gk20a *ch_ctx, 485 struct channel_ctx_gk20a *ch_ctx,
486 u64 addr, u32 size, bool patch) 486 u64 addr, u32 size, bool patch)
487{ 487{
@@ -499,7 +499,7 @@ static void gr_gp10b_commit_global_pagepool(struct gk20a *g,
499 gr_gpcs_gcc_pagepool_total_pages_f(size), patch); 499 gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
500} 500}
501 501
502static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, 502int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
503 struct zbc_entry *color_val, u32 index) 503 struct zbc_entry *color_val, u32 index)
504{ 504{
505 u32 i; 505 u32 i;
@@ -554,7 +554,7 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
554 return 0; 554 return 0;
555} 555}
556 556
557static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, 557int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
558 struct zbc_entry *depth_val, u32 index) 558 struct zbc_entry *depth_val, u32 index)
559{ 559{
560 u32 zbc_z; 560 u32 zbc_z;
@@ -592,12 +592,12 @@ static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
592 return 0; 592 return 0;
593} 593}
594 594
595static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) 595u32 gr_gp10b_pagepool_default_size(struct gk20a *g)
596{ 596{
597 return gr_scc_pagepool_total_pages_hwmax_value_v(); 597 return gr_scc_pagepool_total_pages_hwmax_value_v();
598} 598}
599 599
600static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) 600int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g)
601{ 601{
602 struct gr_gk20a *gr = &g->gr; 602 struct gr_gk20a *gr = &g->gr;
603 int size; 603 int size;
@@ -642,7 +642,7 @@ static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
642 gk20a_dbg_fn("done"); 642 gk20a_dbg_fn("done");
643} 643}
644 644
645static void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data) 645void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data)
646{ 646{
647 u32 val; 647 u32 val;
648 648
@@ -667,7 +667,7 @@ static void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data)
667 gk20a_writel(g, gr_bes_crop_debug3_r(), val); 667 gk20a_writel(g, gr_bes_crop_debug3_r(), val);
668} 668}
669 669
670static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, 670int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
671 u32 class_num, u32 offset, u32 data) 671 u32 class_num, u32 offset, u32 data)
672{ 672{
673 gk20a_dbg_fn(""); 673 gk20a_dbg_fn("");
@@ -718,7 +718,7 @@ fail:
718 return -EINVAL; 718 return -EINVAL;
719} 719}
720 720
721static void gr_gp10b_cb_size_default(struct gk20a *g) 721void gr_gp10b_cb_size_default(struct gk20a *g)
722{ 722{
723 struct gr_gk20a *gr = &g->gr; 723 struct gr_gk20a *gr = &g->gr;
724 724
@@ -728,7 +728,7 @@ static void gr_gp10b_cb_size_default(struct gk20a *g)
728 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 728 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
729} 729}
730 730
731static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 731void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
732{ 732{
733 struct gr_gk20a *gr = &g->gr; 733 struct gr_gk20a *gr = &g->gr;
734 u32 gpc_index, ppc_index, stride, val; 734 u32 gpc_index, ppc_index, stride, val;
@@ -776,7 +776,7 @@ static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
776 } 776 }
777} 777}
778 778
779static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) 779void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
780{ 780{
781 struct gr_gk20a *gr = &g->gr; 781 struct gr_gk20a *gr = &g->gr;
782 u32 gpc_index, ppc_index, stride, val; 782 u32 gpc_index, ppc_index, stride, val;
@@ -843,7 +843,7 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
843 } 843 }
844} 844}
845 845
846static int gr_gp10b_init_ctx_state(struct gk20a *g) 846int gr_gp10b_init_ctx_state(struct gk20a *g)
847{ 847{
848 struct fecs_method_op_gk20a op = { 848 struct fecs_method_op_gk20a op = {
849 .mailbox = { .id = 0, .data = 0, 849 .mailbox = { .id = 0, .data = 0,
@@ -910,7 +910,7 @@ fail_free:
910 return err; 910 return err;
911} 911}
912 912
913static int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, 913int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
914 struct gr_ctx_desc *gr_ctx, 914 struct gr_ctx_desc *gr_ctx,
915 struct vm_gk20a *vm, u32 class, 915 struct vm_gk20a *vm, u32 class,
916 u32 graphics_preempt_mode, 916 u32 graphics_preempt_mode,
@@ -1034,7 +1034,7 @@ fail:
1034 return err; 1034 return err;
1035} 1035}
1036 1036
1037static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, 1037int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
1038 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, 1038 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
1039 u32 class, 1039 u32 class,
1040 u32 flags) 1040 u32 flags)
@@ -1131,7 +1131,7 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
1131 nvgpu_mem_end(g, mem); 1131 nvgpu_mem_end(g, mem);
1132} 1132}
1133 1133
1134static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, 1134void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
1135 struct gr_ctx_desc *gr_ctx) 1135 struct gr_ctx_desc *gr_ctx)
1136{ 1136{
1137 gk20a_dbg_fn(""); 1137 gk20a_dbg_fn("");
@@ -1151,7 +1151,7 @@ static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
1151} 1151}
1152 1152
1153 1153
1154static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, 1154void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
1155 struct channel_ctx_gk20a *ch_ctx, 1155 struct channel_ctx_gk20a *ch_ctx,
1156 struct nvgpu_mem *mem) 1156 struct nvgpu_mem *mem)
1157{ 1157{
@@ -1256,7 +1256,7 @@ out:
1256 gk20a_dbg_fn("done"); 1256 gk20a_dbg_fn("done");
1257} 1257}
1258 1258
1259static int gr_gp10b_dump_gr_status_regs(struct gk20a *g, 1259int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
1260 struct gk20a_debug_output *o) 1260 struct gk20a_debug_output *o)
1261{ 1261{
1262 struct gr_gk20a *gr = &g->gr; 1262 struct gr_gk20a *gr = &g->gr;
@@ -1402,7 +1402,7 @@ static bool gr_activity_empty_or_preempted(u32 val)
1402 return true; 1402 return true;
1403} 1403}
1404 1404
1405static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms, 1405int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1406 u32 expect_delay) 1406 u32 expect_delay)
1407{ 1407{
1408 u32 delay = expect_delay; 1408 u32 delay = expect_delay;
@@ -1453,7 +1453,7 @@ static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1453 return -EAGAIN; 1453 return -EAGAIN;
1454} 1454}
1455 1455
1456static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, 1456void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
1457 struct channel_ctx_gk20a *ch_ctx, 1457 struct channel_ctx_gk20a *ch_ctx,
1458 u64 addr, bool patch) 1458 u64 addr, bool patch)
1459{ 1459{
@@ -1481,7 +1481,7 @@ static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
1481 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); 1481 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch);
1482} 1482}
1483 1483
1484static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g, 1484void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
1485 struct channel_ctx_gk20a *ch_ctx, 1485 struct channel_ctx_gk20a *ch_ctx,
1486 u64 addr, u64 size, bool patch) 1486 u64 addr, u64 size, bool patch)
1487{ 1487{
@@ -1516,7 +1516,7 @@ static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
1516 gr_pd_ab_dist_cfg2_state_limit_f(data), patch); 1516 gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
1517} 1517}
1518 1518
1519static int gr_gp10b_load_smid_config(struct gk20a *g) 1519int gr_gp10b_load_smid_config(struct gk20a *g)
1520{ 1520{
1521 u32 *tpc_sm_id; 1521 u32 *tpc_sm_id;
1522 u32 i, j; 1522 u32 i, j;
@@ -1586,7 +1586,7 @@ int gr_gp10b_init_fs_state(struct gk20a *g)
1586 return gr_gm20b_init_fs_state(g); 1586 return gr_gm20b_init_fs_state(g);
1587} 1587}
1588 1588
1589static void gr_gp10b_init_cyclestats(struct gk20a *g) 1589void gr_gp10b_init_cyclestats(struct gk20a *g)
1590{ 1590{
1591#if defined(CONFIG_GK20A_CYCLE_STATS) 1591#if defined(CONFIG_GK20A_CYCLE_STATS)
1592 g->gpu_characteristics.flags |= 1592 g->gpu_characteristics.flags |=
@@ -1598,7 +1598,7 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g)
1598#endif 1598#endif
1599} 1599}
1600 1600
1601static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 1601void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1602{ 1602{
1603 nvgpu_tegra_fuse_write_bypass(g, 0x1); 1603 nvgpu_tegra_fuse_write_bypass(g, 0x1);
1604 nvgpu_tegra_fuse_write_access_sw(g, 0x0); 1604 nvgpu_tegra_fuse_write_access_sw(g, 0x0);
@@ -1611,7 +1611,7 @@ static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1611 nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); 1611 nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
1612} 1612}
1613 1613
1614static void gr_gp10b_get_access_map(struct gk20a *g, 1614void gr_gp10b_get_access_map(struct gk20a *g,
1615 u32 **whitelist, int *num_entries) 1615 u32 **whitelist, int *num_entries)
1616{ 1616{
1617 static u32 wl_addr_gp10b[] = { 1617 static u32 wl_addr_gp10b[] = {
@@ -1801,7 +1801,7 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g,
1801 * 1801 *
1802 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing 1802 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing
1803 */ 1803 */
1804static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, 1804int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
1805 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, 1805 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
1806 bool sm_debugger_attached, struct channel_gk20a *fault_ch, 1806 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
1807 bool *early_exit, bool *ignore_debugger) 1807 bool *early_exit, bool *ignore_debugger)
@@ -1988,7 +1988,7 @@ clean_up:
1988 return gk20a_gr_handle_fecs_error(g, __ch, isr_data); 1988 return gk20a_gr_handle_fecs_error(g, __ch, isr_data);
1989} 1989}
1990 1990
1991static u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g, 1991u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
1992 u32 gpc, u32 tpc, u32 sm) 1992 u32 gpc, u32 tpc, u32 sm)
1993{ 1993{
1994 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); 1994 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
@@ -2003,7 +2003,7 @@ static u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
2003 return hww_warp_esr; 2003 return hww_warp_esr;
2004} 2004}
2005 2005
2006static u32 get_ecc_override_val(struct gk20a *g) 2006u32 get_ecc_override_val(struct gk20a *g)
2007{ 2007{
2008 u32 val; 2008 u32 val;
2009 2009
@@ -2046,7 +2046,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
2046 return ctx_resident; 2046 return ctx_resident;
2047} 2047}
2048 2048
2049static int gr_gp10b_suspend_contexts(struct gk20a *g, 2049int gr_gp10b_suspend_contexts(struct gk20a *g,
2050 struct dbg_session_gk20a *dbg_s, 2050 struct dbg_session_gk20a *dbg_s,
2051 int *ctx_resident_ch_fd) 2051 int *ctx_resident_ch_fd)
2052{ 2052{
@@ -2122,7 +2122,7 @@ clean_up:
2122 return err; 2122 return err;
2123} 2123}
2124 2124
2125static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, 2125int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
2126 bool boost) 2126 bool boost)
2127{ 2127{
2128 struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx; 2128 struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx;
@@ -2156,7 +2156,7 @@ unmap_ctx:
2156 return err; 2156 return err;
2157} 2157}
2158 2158
2159static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem, 2159void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
2160 struct gr_ctx_desc *gr_ctx) { 2160 struct gr_ctx_desc *gr_ctx) {
2161 u32 v; 2161 u32 v;
2162 2162
@@ -2165,7 +2165,7 @@ static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
2165 nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v); 2165 nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v);
2166} 2166}
2167 2167
2168static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, 2168int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
2169 u32 graphics_preempt_mode, 2169 u32 graphics_preempt_mode,
2170 u32 compute_preempt_mode) 2170 u32 compute_preempt_mode)
2171{ 2171{
@@ -2261,7 +2261,7 @@ unamp_ctx_header:
2261 return err; 2261 return err;
2262} 2262}
2263 2263
2264static int gr_gp10b_get_preemption_mode_flags(struct gk20a *g, 2264int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
2265 struct nvgpu_preemption_modes_rec *preemption_modes_rec) 2265 struct nvgpu_preemption_modes_rec *preemption_modes_rec)
2266{ 2266{
2267 preemption_modes_rec->graphics_preemption_mode_flags = ( 2267 preemption_modes_rec->graphics_preemption_mode_flags = (
@@ -2279,7 +2279,7 @@ static int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
2279 2279
2280 return 0; 2280 return 0;
2281} 2281}
2282static int gp10b_gr_fuse_override(struct gk20a *g) 2282int gp10b_gr_fuse_override(struct gk20a *g)
2283{ 2283{
2284 struct device_node *np = dev_from_gk20a(g)->of_node; 2284 struct device_node *np = dev_from_gk20a(g)->of_node;
2285 u32 *fuses; 2285 u32 *fuses;
@@ -2319,7 +2319,7 @@ static int gp10b_gr_fuse_override(struct gk20a *g)
2319 return 0; 2319 return 0;
2320} 2320}
2321 2321
2322static int gr_gp10b_init_preemption_state(struct gk20a *g) 2322int gr_gp10b_init_preemption_state(struct gk20a *g)
2323{ 2323{
2324 u32 debug_2; 2324 u32 debug_2;
2325 u64 sysclk_rate; 2325 u64 sysclk_rate;
@@ -2341,7 +2341,7 @@ static int gr_gp10b_init_preemption_state(struct gk20a *g)
2341 return 0; 2341 return 0;
2342} 2342}
2343 2343
2344static void gr_gp10b_set_preemption_buffer_va(struct gk20a *g, 2344void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
2345 struct nvgpu_mem *mem, u64 gpu_va) 2345 struct nvgpu_mem *mem, u64 gpu_va)
2346{ 2346{
2347 u32 va = u64_lo32(gpu_va >> 8); 2347 u32 va = u64_lo32(gpu_va >> 8);
@@ -2367,59 +2367,3 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
2367 2367
2368 return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); 2368 return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false);
2369} 2369}
2370
2371void gp10b_init_gr(struct gk20a *g)
2372{
2373 struct gpu_ops *gops = &g->ops;
2374
2375 gm20b_init_gr(g);
2376 gops->gr.init_fs_state = gr_gp10b_init_fs_state;
2377 gops->gr.init_preemption_state = gr_gp10b_init_preemption_state;
2378 gops->gr.is_valid_class = gr_gp10b_is_valid_class;
2379 gops->gr.is_valid_gfx_class = gr_gp10b_is_valid_gfx_class;
2380 gops->gr.is_valid_compute_class = gr_gp10b_is_valid_compute_class;
2381 gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
2382 gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;
2383 gops->gr.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va;
2384 gops->gr.add_zbc_color = gr_gp10b_add_zbc_color;
2385 gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth;
2386 gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size;
2387 gops->gr.calc_global_ctx_buffer_size =
2388 gr_gp10b_calc_global_ctx_buffer_size;
2389 gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb;
2390 gops->gr.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb;
2391 gops->gr.handle_sw_method = gr_gp10b_handle_sw_method;
2392 gops->gr.cb_size_default = gr_gp10b_cb_size_default;
2393 gops->gr.set_alpha_circular_buffer_size =
2394 gr_gp10b_set_alpha_circular_buffer_size;
2395 gops->gr.set_circular_buffer_size =
2396 gr_gp10b_set_circular_buffer_size;
2397 gops->gr.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3;
2398 gops->gr.init_ctx_state = gr_gp10b_init_ctx_state;
2399 gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx;
2400 gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx;
2401 gops->gr.update_ctxsw_preemption_mode =
2402 gr_gp10b_update_ctxsw_preemption_mode;
2403 gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs;
2404 gops->gr.wait_empty = gr_gp10b_wait_empty;
2405 gops->gr.init_cyclestats = gr_gp10b_init_cyclestats;
2406 gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask;
2407 gops->gr.get_access_map = gr_gp10b_get_access_map;
2408 gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception;
2409 gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception;
2410 gops->gr.pre_process_sm_exception =
2411 gr_gp10b_pre_process_sm_exception;
2412 gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error;
2413 gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs;
2414 gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val;
2415 gops->gr.suspend_contexts = gr_gp10b_suspend_contexts;
2416 gops->gr.set_preemption_mode = gr_gp10b_set_preemption_mode;
2417 gops->gr.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode;
2418 gops->gr.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags;
2419 gops->gr.fuse_override = gp10b_gr_fuse_override;
2420 gops->gr.load_smid_config = gr_gp10b_load_smid_config;
2421 gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx;
2422 gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx;
2423 gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass;
2424 gops->gr.get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr;
2425}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index ac53e231..ce1ca01f 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -20,6 +20,10 @@
20 20
21struct gk20a; 21struct gk20a;
22struct gr_gk20a_isr_data; 22struct gr_gk20a_isr_data;
23struct channel_ctx_gk20a;
24struct zbc_entry;
25struct gr_ctx_desc;
26struct nvgpu_preemption_modes_rec;
23 27
24enum { 28enum {
25 PASCAL_CHANNEL_GPFIFO_A = 0xC06F, 29 PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
@@ -39,7 +43,6 @@ enum {
39#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 43#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
40#define NVC0C0_SET_RD_COALESCE 0x0228 44#define NVC0C0_SET_RD_COALESCE 0x0228
41 45
42void gp10b_init_gr(struct gk20a *g);
43int gr_gp10b_init_fs_state(struct gk20a *g); 46int gr_gp10b_init_fs_state(struct gk20a *g);
44int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, 47int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
45 struct nvgpu_mem *mem); 48 struct nvgpu_mem *mem);
@@ -50,6 +53,87 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g,
50int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, 53int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
51 struct channel_gk20a *fault_ch); 54 struct channel_gk20a *fault_ch);
52 55
56bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num);
57bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
58bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num);
59int gr_gp10b_handle_sm_exception(struct gk20a *g,
60 u32 gpc, u32 tpc, u32 sm,
61 bool *post_event, struct channel_gk20a *fault_ch,
62 u32 *hww_global_esr);
63int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
64 bool *post_event);
65int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
66 struct channel_gk20a *c, bool patch);
67void gr_gp10b_commit_global_pagepool(struct gk20a *g,
68 struct channel_ctx_gk20a *ch_ctx,
69 u64 addr, u32 size, bool patch);
70int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
71 struct zbc_entry *color_val, u32 index);
72int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
73 struct zbc_entry *depth_val, u32 index);
74u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
75int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
76void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
77int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
78 u32 class_num, u32 offset, u32 data);
79void gr_gp10b_cb_size_default(struct gk20a *g);
80void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
81void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
82int gr_gp10b_init_ctx_state(struct gk20a *g);
83int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
84 struct gr_ctx_desc *gr_ctx,
85 struct vm_gk20a *vm, u32 class,
86 u32 graphics_preempt_mode,
87 u32 compute_preempt_mode);
88int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
89 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
90 u32 class,
91 u32 flags);
92void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
93 struct gr_ctx_desc *gr_ctx);
94void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
95 struct channel_ctx_gk20a *ch_ctx,
96 struct nvgpu_mem *mem);
97int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
98 struct gk20a_debug_output *o);
99int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
100 u32 expect_delay);
101void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
102 struct channel_ctx_gk20a *ch_ctx,
103 u64 addr, bool patch);
104void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
105 struct channel_ctx_gk20a *ch_ctx,
106 u64 addr, u64 size, bool patch);
107int gr_gp10b_load_smid_config(struct gk20a *g);
108void gr_gp10b_init_cyclestats(struct gk20a *g);
109void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
110void gr_gp10b_get_access_map(struct gk20a *g,
111 u32 **whitelist, int *num_entries);
112int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
113 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
114 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
115 bool *early_exit, bool *ignore_debugger);
116u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
117 u32 gpc, u32 tpc, u32 sm);
118u32 get_ecc_override_val(struct gk20a *g);
119int gr_gp10b_suspend_contexts(struct gk20a *g,
120 struct dbg_session_gk20a *dbg_s,
121 int *ctx_resident_ch_fd);
122int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
123 bool boost);
124void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
125 struct gr_ctx_desc *gr_ctx);
126int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
127 u32 graphics_preempt_mode,
128 u32 compute_preempt_mode);
129int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
130 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
131int gp10b_gr_fuse_override(struct gk20a *g);
132int gr_gp10b_init_preemption_state(struct gk20a *g);
133void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
134 struct nvgpu_mem *mem, u64 gpu_va);
135int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
136
53struct gr_t18x { 137struct gr_t18x {
54 struct { 138 struct {
55 u32 preempt_image_size; 139 u32 preempt_image_size;
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 69a90031..d0f07a2b 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -27,6 +27,7 @@
27#include "gk20a/mc_gk20a.h" 27#include "gk20a/mc_gk20a.h"
28#include "gk20a/fb_gk20a.h" 28#include "gk20a/fb_gk20a.h"
29#include "gk20a/pmu_gk20a.h" 29#include "gk20a/pmu_gk20a.h"
30#include "gk20a/gr_gk20a.h"
30 31
31#include "gp10b/gr_gp10b.h" 32#include "gp10b/gr_gp10b.h"
32#include "gp10b/fecs_trace_gp10b.h" 33#include "gp10b/fecs_trace_gp10b.h"
@@ -179,6 +180,128 @@ static const struct gpu_ops gp10b_ops = {
179 .isr_stall = gp10b_ce_isr, 180 .isr_stall = gp10b_ce_isr,
180 .isr_nonstall = gp10b_ce_nonstall_isr, 181 .isr_nonstall = gp10b_ce_nonstall_isr,
181 }, 182 },
183 .gr = {
184 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
185 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
186 .cb_size_default = gr_gp10b_cb_size_default,
187 .calc_global_ctx_buffer_size =
188 gr_gp10b_calc_global_ctx_buffer_size,
189 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
190 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
191 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
192 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
193 .handle_sw_method = gr_gp10b_handle_sw_method,
194 .set_alpha_circular_buffer_size =
195 gr_gp10b_set_alpha_circular_buffer_size,
196 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
197 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
198 .is_valid_class = gr_gp10b_is_valid_class,
199 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
200 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
201 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
202 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
203 .init_fs_state = gr_gp10b_init_fs_state,
204 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
205 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
206 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
207 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
208 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
209 .free_channel_ctx = gk20a_free_channel_ctx,
210 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
211 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
212 .get_zcull_info = gr_gk20a_get_zcull_info,
213 .is_tpc_addr = gr_gm20b_is_tpc_addr,
214 .get_tpc_num = gr_gm20b_get_tpc_num,
215 .detect_sm_arch = gr_gm20b_detect_sm_arch,
216 .add_zbc_color = gr_gp10b_add_zbc_color,
217 .add_zbc_depth = gr_gp10b_add_zbc_depth,
218 .zbc_set_table = gk20a_gr_zbc_set_table,
219 .zbc_query_table = gr_gk20a_query_zbc,
220 .pmu_save_zbc = gk20a_pmu_save_zbc,
221 .add_zbc = gr_gk20a_add_zbc,
222 .pagepool_default_size = gr_gp10b_pagepool_default_size,
223 .init_ctx_state = gr_gp10b_init_ctx_state,
224 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
225 .free_gr_ctx = gr_gp10b_free_gr_ctx,
226 .update_ctxsw_preemption_mode =
227 gr_gp10b_update_ctxsw_preemption_mode,
228 .dump_gr_regs = gr_gp10b_dump_gr_status_regs,
229 .update_pc_sampling = gr_gm20b_update_pc_sampling,
230 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
231 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
232 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
233 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
234 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
235 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
236 .wait_empty = gr_gp10b_wait_empty,
237 .init_cyclestats = gr_gp10b_init_cyclestats,
238 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
239 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
240 .bpt_reg_info = gr_gm20b_bpt_reg_info,
241 .get_access_map = gr_gp10b_get_access_map,
242 .handle_fecs_error = gr_gp10b_handle_fecs_error,
243 .handle_sm_exception = gr_gp10b_handle_sm_exception,
244 .handle_tex_exception = gr_gp10b_handle_tex_exception,
245 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
246 .enable_exceptions = gk20a_gr_enable_exceptions,
247 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
248 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
249 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
250 .record_sm_error_state = gm20b_gr_record_sm_error_state,
251 .update_sm_error_state = gm20b_gr_update_sm_error_state,
252 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
253 .suspend_contexts = gr_gp10b_suspend_contexts,
254 .resume_contexts = gr_gk20a_resume_contexts,
255 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
256 .fuse_override = gp10b_gr_fuse_override,
257 .init_sm_id_table = gr_gk20a_init_sm_id_table,
258 .load_smid_config = gr_gp10b_load_smid_config,
259 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
260 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
261 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
262 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
263 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
264 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
265 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
266 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
267 .commit_inst = gr_gk20a_commit_inst,
268 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
269 .write_pm_ptr = gr_gk20a_write_pm_ptr,
270 .init_elcg_mode = gr_gk20a_init_elcg_mode,
271 .load_tpc_mask = gr_gm20b_load_tpc_mask,
272 .inval_icache = gr_gk20a_inval_icache,
273 .trigger_suspend = gr_gk20a_trigger_suspend,
274 .wait_for_pause = gr_gk20a_wait_for_pause,
275 .resume_from_pause = gr_gk20a_resume_from_pause,
276 .clear_sm_errors = gr_gk20a_clear_sm_errors,
277 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
278 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
279 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
280 .suspend_single_sm = gk20a_gr_suspend_single_sm,
281 .suspend_all_sms = gk20a_gr_suspend_all_sms,
282 .resume_single_sm = gk20a_gr_resume_single_sm,
283 .resume_all_sms = gk20a_gr_resume_all_sms,
284 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
285 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
286 .get_sm_no_lock_down_hww_global_esr_mask =
287 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
288 .lock_down_sm = gk20a_gr_lock_down_sm,
289 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
290 .clear_sm_hww = gm20b_gr_clear_sm_hww,
291 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
292 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
293 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
294 .set_boosted_ctx = gr_gp10b_set_boosted_ctx,
295 .set_preemption_mode = gr_gp10b_set_preemption_mode,
296 .set_czf_bypass = gr_gp10b_set_czf_bypass,
297 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
298 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
299 .init_preemption_state = gr_gp10b_init_preemption_state,
300 .update_boosted_ctx = gr_gp10b_update_boosted_ctx,
301 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
302 .create_gr_sysfs = gr_gp10b_create_sysfs,
303 .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
304 },
182 .fb = { 305 .fb = {
183 .reset = fb_gk20a_reset, 306 .reset = fb_gk20a_reset,
184 .init_hw = gk20a_fb_init_hw, 307 .init_hw = gk20a_fb_init_hw,
@@ -474,6 +597,7 @@ int gp10b_init_hal(struct gk20a *g)
474 597
475 gops->ltc = gp10b_ops.ltc; 598 gops->ltc = gp10b_ops.ltc;
476 gops->ce2 = gp10b_ops.ce2; 599 gops->ce2 = gp10b_ops.ce2;
600 gops->gr = gp10b_ops.gr;
477 gops->fb = gp10b_ops.fb; 601 gops->fb = gp10b_ops.fb;
478 gops->clock_gating = gp10b_ops.clock_gating; 602 gops->clock_gating = gp10b_ops.clock_gating;
479 gops->fifo = gp10b_ops.fifo; 603 gops->fifo = gp10b_ops.fifo;
@@ -564,6 +688,8 @@ int gp10b_init_hal(struct gk20a *g)
564 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; 688 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
565 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; 689 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
566 gops->pmu.is_priv_load = gp10b_is_priv_load; 690 gops->pmu.is_priv_load = gp10b_is_priv_load;
691
692 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
567 } else { 693 } else {
568 /* Inherit from gk20a */ 694 /* Inherit from gk20a */
569 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, 695 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
@@ -574,12 +700,13 @@ int gp10b_init_hal(struct gk20a *g)
574 gops->pmu.load_lsfalcon_ucode = NULL; 700 gops->pmu.load_lsfalcon_ucode = NULL;
575 gops->pmu.init_wpr_region = NULL; 701 gops->pmu.init_wpr_region = NULL;
576 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; 702 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
703
704 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
577 } 705 }
578 706
579 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 707 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
580 g->pmu_lsf_pmu_wpr_init_done = 0; 708 g->pmu_lsf_pmu_wpr_init_done = 0;
581 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; 709 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
582 gp10b_init_gr(g);
583 710
584 gp10b_init_uncompressed_kind_map(); 711 gp10b_init_uncompressed_kind_map();
585 gp10b_init_kind_attr(); 712 gp10b_init_kind_attr();
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:49:35 -0400