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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-03-17 14:09:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-23 11:44:07 -0400
commit4492c62ffe9398bd4457f6f1c2773e40afe909fb (patch)
tree5d792f81d97844278f4eca665a8b4778fa93dc35 /drivers/gpu/nvgpu/gp10b
parent33f637585ecd617a9f4423f56e2aa6df0691ac64 (diff)
gpu: nvgpu: Add bus HAL
Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c3
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c2
3 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 62a19abd..245d2d26 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -21,6 +21,7 @@
21#include "gk20a/gk20a.h" 21#include "gk20a/gk20a.h"
22#include "gk20a/dbg_gpu_gk20a.h" 22#include "gk20a/dbg_gpu_gk20a.h"
23#include "gk20a/css_gr_gk20a.h" 23#include "gk20a/css_gr_gk20a.h"
24#include "gk20a/bus_gk20a.h"
24 25
25#include "gp10b/gr_gp10b.h" 26#include "gp10b/gr_gp10b.h"
26#include "gp10b/fecs_trace_gp10b.h" 27#include "gp10b/fecs_trace_gp10b.h"
@@ -232,6 +233,7 @@ int gp10b_init_hal(struct gk20a *g)
232 } 233 }
233#endif 234#endif
234 235
236 gk20a_init_bus(gops);
235 gp10b_init_mc(gops); 237 gp10b_init_mc(gops);
236 gp10b_init_gr(gops); 238 gp10b_init_gr(gops);
237 gp10b_init_fecs_trace_ops(gops); 239 gp10b_init_fecs_trace_ops(gops);
@@ -254,7 +256,6 @@ int gp10b_init_hal(struct gk20a *g)
254 gops->name = "gp10b"; 256 gops->name = "gp10b";
255 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; 257 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
256 gops->get_litter_value = gp10b_get_litter_value; 258 gops->get_litter_value = gp10b_get_litter_value;
257 gops->read_ptimer = gk20a_read_ptimer;
258 259
259 c->twod_class = FERMI_TWOD_A; 260 c->twod_class = FERMI_TWOD_A;
260 c->threed_class = PASCAL_A; 261 c->threed_class = PASCAL_A;
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index fc0e6553..547169ed 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -162,7 +162,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
162 if (mc_intr_0 & mc_intr_ltc_pending_f()) 162 if (mc_intr_0 & mc_intr_ltc_pending_f())
163 g->ops.ltc.isr(g); 163 g->ops.ltc.isr(g);
164 if (mc_intr_0 & mc_intr_pbus_pending_f()) 164 if (mc_intr_0 & mc_intr_pbus_pending_f())
165 gk20a_pbus_isr(g); 165 g->ops.bus.isr(g);
166 166
167 /* sync handled irq counter before re-enabling interrupts */ 167 /* sync handled irq counter before re-enabling interrupts */
168 atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); 168 atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 26facbe3..a5322bad 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -45,7 +45,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g)
45 (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) 45 (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
46 >> 8ULL)); 46 >> 8ULL));
47 47
48 g->ops.mm.bar1_bind(g, inst_block); 48 g->ops.bus.bar1_bind(g, inst_block);
49 49
50 if (g->ops.mm.init_bar2_mm_hw_setup) { 50 if (g->ops.mm.init_bar2_mm_hw_setup) {
51 err = g->ops.mm.init_bar2_mm_hw_setup(g); 51 err = g->ops.mm.init_bar2_mm_hw_setup(g);