gpu: nvgpu: gp10b: Add litter values HAL

Move per-chip constants to be returned by a chip specific function.
Implement get_litter_value() for each chip.

Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1121384
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>

3 files changed, 108 insertions, 26 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1aba35f3..6ab8e923 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -25,7 +25,6 @@
 #include "gp10b/gr_gp10b.h"
 #include "hw_gr_gp10b.h"
 #include "hw_fifo_gp10b.h"
-#include "hw_proj_gp10b.h"
 #include "hw_ctxsw_prog_gp10b.h"
 #include "hw_mc_gp10b.h"
 #include "gp10b_sysfs.h"
@@ -61,8 +60,9 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                         bool *post_event, struct channel_gk20a *fault_ch)
 {
         int ret = 0;
-        u32 offset = proj_gpc_stride_v() * gpc +
-                        proj_tpc_in_gpc_stride_v() * tpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+        u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
         u32 lrf_ecc_status, shm_ecc_status;
 
         gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch);
@@ -170,8 +170,9 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 bool *post_event)
 {
         int ret = 0;
-        u32 offset = proj_gpc_stride_v() * gpc +
-                     proj_tpc_in_gpc_stride_v() * tpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+        u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
         u32 esr;
         u32 ecc_stats_reg_val;
 
@@ -314,6 +315,9 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
         u32 temp, temp2;
         u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate;
         u32 attrib_size_in_chunk, cb_attrib_cache_size_init;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
+        u32 num_pes_per_gpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_PES_PER_GPC);
 
         gk20a_dbg_fn("");
 
@@ -346,8 +350,8 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
                 gr->tpc_count * gr->alpha_cb_size;
 
         for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
-                temp = proj_gpc_stride_v() * gpc_index;
-                temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index;
+                temp = gpc_stride * gpc_index;
+                temp2 = num_pes_per_gpc * gpc_index;
                 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
                      ppc_index++) {
                         cbm_cfg_size_beta = cb_attrib_cache_size_init *
@@ -359,17 +363,17 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
 
                         gr_gk20a_ctx_patch_write(g, ch_ctx,
                                 gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp +
-                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                ppc_in_gpc_stride * ppc_index,
                                 cbm_cfg_size_beta, patch);
 
                         gr_gk20a_ctx_patch_write(g, ch_ctx,
                                 gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp +
-                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                ppc_in_gpc_stride * ppc_index,
                                 attrib_offset_in_chunk, patch);
 
                         gr_gk20a_ctx_patch_write(g, ch_ctx,
                                 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
-                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                ppc_in_gpc_stride * ppc_index,
                                 cbm_cfg_size_steadystate,
                                 patch);
 
@@ -378,12 +382,12 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
 
                         gr_gk20a_ctx_patch_write(g, ch_ctx,
                                 gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp +
-                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                ppc_in_gpc_stride * ppc_index,
                                 cbm_cfg_size_alpha, patch);
 
                         gr_gk20a_ctx_patch_write(g, ch_ctx,
                                 gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp +
-                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                ppc_in_gpc_stride * ppc_index,
                                 alpha_offset_in_chunk, patch);
 
                         alpha_offset_in_chunk += gr->alpha_cb_size *
@@ -618,6 +622,8 @@ static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
         u32 gpc_index, ppc_index, stride, val;
         u32 pd_ab_max_output;
         u32 alpha_cb_size = data * 4;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
 
         gk20a_dbg_fn("");
 
@@ -638,14 +644,14 @@ static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
                 gr_pd_ab_dist_cfg1_max_batches_init_f());
 
         for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
-                stride = proj_gpc_stride_v() * gpc_index;
+                stride = gpc_stride * gpc_index;
 
                 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
                         ppc_index++) {
 
                         val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
                                 stride +
-                                proj_ppc_in_gpc_stride_v() * ppc_index);
+                                ppc_in_gpc_stride * ppc_index);
 
                         val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(),
                                         gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size *
@@ -653,7 +659,7 @@ static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
 
                         gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
                                 stride +
-                                proj_ppc_in_gpc_stride_v() * ppc_index, val);
+                                ppc_in_gpc_stride * ppc_index, val);
                 }
         }
 }
@@ -663,6 +669,8 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
         struct gr_gk20a *gr = &g->gr;
         u32 gpc_index, ppc_index, stride, val;
         u32 cb_size_steady = data * 4, cb_size;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
 
         gk20a_dbg_fn("");
 
@@ -684,14 +692,14 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
                  gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady));
 
         for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
-                stride = proj_gpc_stride_v() * gpc_index;
+                stride = gpc_stride * gpc_index;
 
                 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
                         ppc_index++) {
 
                         val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
                                 stride +
-                                proj_ppc_in_gpc_stride_v() * ppc_index);
+                                ppc_in_gpc_stride * ppc_index);
 
                         val = set_field(val,
                                 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(),
@@ -700,9 +708,9 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
 
                         gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
                                 stride +
-                                proj_ppc_in_gpc_stride_v() * ppc_index, val);
+                                ppc_in_gpc_stride * ppc_index, val);
 
-                        gk20a_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index +
+                        gk20a_writel(g, ppc_in_gpc_stride * ppc_index +
                                 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() +
                                 stride,
                                 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(
@@ -1542,8 +1550,9 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
         bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode ==
                         NVGPU_GR_PREEMPTION_MODE_CILP) ;
         u32 global_mask = 0, dbgr_control0, global_esr_copy;
-        u32 offset = proj_gpc_stride_v() * gpc +
-                     proj_tpc_in_gpc_stride_v() * tpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+        u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 
         *early_exit = false;
         *ignore_debugger = false;
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 427936c7..ea5e3f15 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -42,6 +42,7 @@
 #include <linux/tegra-fuse.h>
 
 #include "gp10b.h"
+#include "hw_proj_gp10b.h"
 
 #define FUSE_OPT_PRIV_SEC_EN_0 0x264
 #define PRIV_SECURITY_ENABLED 0x01
@@ -99,6 +100,78 @@ static struct gpu_ops gp10b_ops = {
         }
 };
 
+static int gp10b_get_litter_value(struct gk20a *g,
+                enum nvgpu_litter_value value)
+{
+        int ret = EINVAL;
+        switch (value) {
+        case GPU_LIT_NUM_GPCS:
+                ret = proj_scal_litter_num_gpcs_v();
+                break;
+        case GPU_LIT_NUM_PES_PER_GPC:
+                ret = proj_scal_litter_num_pes_per_gpc_v();
+                break;
+        case GPU_LIT_NUM_ZCULL_BANKS:
+                ret = proj_scal_litter_num_zcull_banks_v();
+                break;
+        case GPU_LIT_NUM_TPC_PER_GPC:
+                ret = proj_scal_litter_num_tpc_per_gpc_v();
+                break;
+        case GPU_LIT_NUM_FBPS:
+                ret = proj_scal_litter_num_fbps_v();
+                break;
+        case GPU_LIT_GPC_BASE:
+                ret = proj_gpc_base_v();
+                break;
+        case GPU_LIT_GPC_STRIDE:
+                ret = proj_gpc_stride_v();
+                break;
+        case GPU_LIT_GPC_SHARED_BASE:
+                ret = proj_gpc_shared_base_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_BASE:
+                ret = proj_tpc_in_gpc_base_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_STRIDE:
+                ret = proj_tpc_in_gpc_stride_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+                ret = proj_tpc_in_gpc_shared_base_v();
+                break;
+        case GPU_LIT_PPC_IN_GPC_STRIDE:
+                ret = proj_ppc_in_gpc_stride_v();
+                break;
+        case GPU_LIT_ROP_BASE:
+                ret = proj_rop_base_v();
+                break;
+        case GPU_LIT_ROP_STRIDE:
+                ret = proj_rop_stride_v();
+                break;
+        case GPU_LIT_ROP_SHARED_BASE:
+                ret = proj_rop_shared_base_v();
+                break;
+        case GPU_LIT_HOST_NUM_PBDMA:
+                ret = proj_host_num_pbdma_v();
+                break;
+        case GPU_LIT_LTC_STRIDE:
+                ret = proj_ltc_stride_v();
+                break;
+        case GPU_LIT_LTS_STRIDE:
+                ret = proj_lts_stride_v();
+                break;
+        case GPU_LIT_NUM_FBPAS:
+                ret = proj_scal_litter_num_fbpas_v();
+                break;
+        case GPU_LIT_FBPA_STRIDE:
+                ret = proj_fbpa_stride_v();
+                break;
+        default:
+                break;
+        }
+
+        return ret;
+}
+
 int gp10b_init_hal(struct gk20a *g)
 {
         struct gpu_ops *gops = &g->ops;
@@ -156,6 +229,7 @@ int gp10b_init_hal(struct gk20a *g)
         gp10b_init_therm_ops(gops);
         gops->name = "gp10b";
         gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
+        gops->get_litter_value = gp10b_get_litter_value;
 
         c->twod_class = FERMI_TWOD_A;
         c->threed_class = PASCAL_A;
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index e68e762d..92735f1a 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -19,7 +19,6 @@
 
 #include "gk20a/gk20a.h"
 #include "gm20b/ltc_gm20b.h"
-#include "hw_proj_gp10b.h"
 #include "hw_mc_gp10b.h"
 #include "hw_ltc_gp10b.h"
 
@@ -125,6 +124,8 @@ static void gp10b_ltc_isr(struct gk20a *g)
 {
         u32 mc_intr, ltc_intr;
         int ltc, slice;
+        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
 
         mc_intr = gk20a_readl(g, mc_intr_ltc_r());
         gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x",
@@ -133,8 +134,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
                 if ((mc_intr & 1 << ltc) == 0)
                         continue;
                 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
-                        u32 offset = proj_ltc_stride_v() * ltc +
-                                        proj_lts_stride_v() * slice;
+                        u32 offset = ltc_stride * ltc + lts_stride * slice;
                         ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
 
                         /* Detect and handle ECC errors */
@@ -180,8 +180,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
                         gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x",
                                   ltc, slice, ltc_intr);
                         gk20a_writel(g, ltc_ltc0_lts0_intr_r() +
-                                           proj_ltc_stride_v() * ltc +
-                                           proj_lts_stride_v() * slice,
+                                           ltc_stride * ltc + lts_stride * slice,
                                      ltc_intr);
                 }
         }