gpu: nvgpu: resolve MISRA 10.3 violations

MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.

This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.

JIRA NVGPU-647

Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 19 insertions, 19 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
index 60f36b6c..8113f7d5 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -382,7 +382,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
         { 0x009a0100,   1},
 };
 
-static const u32 gp10b_global_whitelist_ranges_count =
+static const u64 gp10b_global_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_global_whitelist_ranges);
 
 /* context */
@@ -390,24 +390,24 @@ static const u32 gp10b_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gp10b_runcontrol_whitelist[] = {
 };
-static const u32 gp10b_runcontrol_whitelist_count =
+static const u64 gp10b_runcontrol_whitelist_count =
         ARRAY_SIZE(gp10b_runcontrol_whitelist);
 
 static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gp10b_runcontrol_whitelist_ranges_count =
+static const u64 gp10b_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gp10b_qctl_whitelist[] = {
 };
-static const u32 gp10b_qctl_whitelist_count =
+static const u64 gp10b_qctl_whitelist_count =
         ARRAY_SIZE(gp10b_qctl_whitelist);
 
 static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
 };
-static const u32 gp10b_qctl_whitelist_ranges_count =
+static const u64 gp10b_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
@@ -415,7 +415,7 @@ const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
         return gp10b_global_whitelist_ranges;
 }
 
-int gp10b_get_global_whitelist_ranges_count(void)
+u64 gp10b_get_global_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
@@ -425,7 +425,7 @@ const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
         return gp10b_global_whitelist_ranges;
 }
 
-int gp10b_get_context_whitelist_ranges_count(void)
+u64 gp10b_get_context_whitelist_ranges_count(void)
 {
         return gp10b_global_whitelist_ranges_count;
 }
@@ -435,7 +435,7 @@ const u32 *gp10b_get_runcontrol_whitelist(void)
         return gp10b_runcontrol_whitelist;
 }
 
-int gp10b_get_runcontrol_whitelist_count(void)
+u64 gp10b_get_runcontrol_whitelist_count(void)
 {
         return gp10b_runcontrol_whitelist_count;
 }
@@ -445,7 +445,7 @@ const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
         return gp10b_runcontrol_whitelist_ranges;
 }
 
-int gp10b_get_runcontrol_whitelist_ranges_count(void)
+u64 gp10b_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp10b_runcontrol_whitelist_ranges_count;
 }
@@ -455,7 +455,7 @@ const u32 *gp10b_get_qctl_whitelist(void)
         return gp10b_qctl_whitelist;
 }
 
-int gp10b_get_qctl_whitelist_count(void)
+u64 gp10b_get_qctl_whitelist_count(void)
 {
         return gp10b_qctl_whitelist_count;
 }
@@ -465,7 +465,7 @@ const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
         return gp10b_qctl_whitelist_ranges;
 }
 
-int gp10b_get_qctl_whitelist_ranges_count(void)
+u64 gp10b_get_qctl_whitelist_ranges_count(void)
 {
         return gp10b_qctl_whitelist_ranges_count;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
index 7bc08189..e8b9f325 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -2,7 +2,7 @@
  *
  * Tegra GP10B GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,17 +28,17 @@
 struct dbg_session_gk20a;
 
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
-int gp10b_get_global_whitelist_ranges_count(void);
+u64 gp10b_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
-int gp10b_get_context_whitelist_ranges_count(void);
+u64 gp10b_get_context_whitelist_ranges_count(void);
 const u32 *gp10b_get_runcontrol_whitelist(void);
-int gp10b_get_runcontrol_whitelist_count(void);
+u64 gp10b_get_runcontrol_whitelist_count(void);
 const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
-int gp10b_get_runcontrol_whitelist_ranges_count(void);
+u64 gp10b_get_runcontrol_whitelist_ranges_count(void);
 const u32 *gp10b_get_qctl_whitelist(void);
-int gp10b_get_qctl_whitelist_count(void);
+u64 gp10b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
-int gp10b_get_qctl_whitelist_ranges_count(void);
+u64 gp10b_get_qctl_whitelist_ranges_count(void);
 int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* __REGOPS_GP10B_H_ */