gpu: nvgpu: Implement bus HAL for bar2 bind

Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.

JIRA NVGPU-588

Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 4 insertions, 29 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 934ddb9a..8cd2a582 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -26,6 +26,7 @@
 #include "common/clock_gating/gp10b_gating_reglist.h"
 #include "common/ptimer/ptimer_gk20a.h"
 #include "common/bus/bus_gm20b.h"
+#include "common/bus/bus_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -554,7 +555,6 @@ static const struct gpu_ops gp10b_ops = {
                 .init_inst_block = gk20a_init_inst_block,
                 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
                 .init_bar2_vm = gp10b_init_bar2_vm,
-                .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup,
                 .remove_bar2_vm = gp10b_remove_bar2_vm,
                 .get_kind_invalid = gm20b_get_kind_invalid,
                 .get_kind_pitch = gm20b_get_kind_pitch,
@@ -653,6 +653,7 @@ static const struct gpu_ops gp10b_ops = {
                 .init_hw = gk20a_bus_init_hw,
                 .isr = gk20a_bus_isr,
                 .bar1_bind = gm20b_bus_bar1_bind,
+                .bar2_bind = gp10b_bus_bar2_bind,
                 .set_bar0_window = gk20a_bus_set_bar0_window,
         },
         .ptimer = {
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index acd42dd8..50c96f36 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -34,7 +34,6 @@
 
 #include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_bus_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
 
 u32 gp10b_mm_get_default_big_page_size(void)
@@ -62,8 +61,8 @@ int gp10b_init_mm_setup_hw(struct gk20a *g)
 
         g->ops.bus.bar1_bind(g, inst_block);
 
-        if (g->ops.mm.init_bar2_mm_hw_setup) {
-                err = g->ops.mm.init_bar2_mm_hw_setup(g);
+        if (g->ops.bus.bar2_bind) {
+                err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block);
                 if (err)
                         return err;
         }
@@ -109,29 +108,6 @@ clean_up_va:
         return err;
 }
 
-int gp10b_init_bar2_mm_hw_setup(struct gk20a *g)
-{
-        struct mm_gk20a *mm = &g->mm;
-        struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
-        u64 inst_pa = nvgpu_inst_block_addr(g, inst_block);
-
-        nvgpu_log_fn(g, " ");
-
-        inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v());
-        nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x",  (u32)inst_pa);
-
-        gk20a_writel(g, bus_bar2_block_r(),
-                     nvgpu_aperture_mask(g, inst_block,
-                                         bus_bar2_block_target_sys_mem_ncoh_f(),
-                                         bus_bar2_block_target_sys_mem_coh_f(),
-                                         bus_bar2_block_target_vid_mem_f()) |
-                     bus_bar2_block_mode_virtual_f() |
-                     bus_bar2_block_ptr_f(inst_pa));
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-}
-
 static void update_gmmu_pde3_locked(struct vm_gk20a *vm,
                                     const struct gk20a_mmu_level *l,
                                     struct nvgpu_gmmu_pd *pd,
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
index 5522d02e..4f37aae6 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
@@ -32,7 +32,6 @@ u32 gp10b_mm_get_default_big_page_size(void);
 u32 gp10b_mm_get_iommu_bit(struct gk20a *g);
 int gp10b_init_mm_setup_hw(struct gk20a *g);
 int gp10b_init_bar2_vm(struct gk20a *g);
-int gp10b_init_bar2_mm_hw_setup(struct gk20a *g);
 const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
         u32 big_page_size);
 void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
index 3f089545..7a714441 100644
--- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
@@ -30,7 +30,6 @@
 
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_bus_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
 
 int gp10b_replayable_pagefault_buffer_init(struct gk20a *g)