diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-11-03 03:37:29 -0500 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:02 -0500 |
commit | 23a4456260f163881b54b89fc14ec14a2b0d1f35 (patch) | |
tree | ad07f5c8a1e2b9b155d00cde6eca6d9ccaddec85 /drivers/gpu/nvgpu/gp10b | |
parent | 1e4861a347eb4ae602ff494596bacf01a6ddd4cc (diff) |
gpu: nvgpu: gp10b: Add SM debug registers
Add SM debug registers to gp10b, and regenerate headers.
Bug 1567274
Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592646
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 4 |
3 files changed, 67 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 161c1ce0..f6020434 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | |||
@@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) | |||
200 | } | 200 | } |
201 | static inline u32 gmmu_pte_comptagline_f(u32 v) | 201 | static inline u32 gmmu_pte_comptagline_f(u32 v) |
202 | { | 202 | { |
203 | return (v & 0x1ffff) << 12; | 203 | return (v & 0x3ffff) << 12; |
204 | } | 204 | } |
205 | static inline u32 gmmu_pte_comptagline_w(void) | 205 | static inline u32 gmmu_pte_comptagline_w(void) |
206 | { | 206 | { |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 9b681104..f314c75c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -2814,6 +2814,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | |||
2814 | { | 2814 | { |
2815 | return 0x80000000; | 2815 | return 0x80000000; |
2816 | } | 2816 | } |
2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | ||
2818 | { | ||
2819 | return 0x0; | ||
2820 | } | ||
2821 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | ||
2822 | { | ||
2823 | return 0x40000000; | ||
2824 | } | ||
2817 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 2825 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
2818 | { | 2826 | { |
2819 | return 0x0050460c; | 2827 | return 0x0050460c; |
@@ -2826,6 +2834,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) | |||
2826 | { | 2834 | { |
2827 | return 0x00000001; | 2835 | return 0x00000001; |
2828 | } | 2836 | } |
2837 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) | ||
2838 | { | ||
2839 | return 0x00419e50; | ||
2840 | } | ||
2841 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) | ||
2842 | { | ||
2843 | return 0x10; | ||
2844 | } | ||
2845 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) | ||
2846 | { | ||
2847 | return 0x20; | ||
2848 | } | ||
2849 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) | ||
2850 | { | ||
2851 | return 0x40; | ||
2852 | } | ||
2829 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 2853 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
2830 | { | 2854 | { |
2831 | return 0x00504650; | 2855 | return 0x00504650; |
@@ -3226,4 +3250,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | |||
3226 | { | 3250 | { |
3227 | return 0x004188ac; | 3251 | return 0x004188ac; |
3228 | } | 3252 | } |
3253 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | ||
3254 | { | ||
3255 | return 0x00419e10; | ||
3256 | } | ||
3257 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | ||
3258 | { | ||
3259 | return (v & 0x1) << 0; | ||
3260 | } | ||
3261 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | ||
3262 | { | ||
3263 | return 0x00000001; | ||
3264 | } | ||
3265 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | ||
3266 | { | ||
3267 | return 0x1 << 31; | ||
3268 | } | ||
3269 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3270 | { | ||
3271 | return (r >> 31) & 0x1; | ||
3272 | } | ||
3273 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | ||
3274 | { | ||
3275 | return 0x80000000; | ||
3276 | } | ||
3277 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | ||
3278 | { | ||
3279 | return 0x0; | ||
3280 | } | ||
3281 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | ||
3282 | { | ||
3283 | return 0x1 << 30; | ||
3284 | } | ||
3285 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | ||
3286 | { | ||
3287 | return (r >> 30) & 0x1; | ||
3288 | } | ||
3289 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) | ||
3290 | { | ||
3291 | return 0x40000000; | ||
3292 | } | ||
3229 | #endif | 3293 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index a38cfe8d..68f5a128 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | |||
@@ -124,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | |||
124 | } | 124 | } |
125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | 125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) |
126 | { | 126 | { |
127 | return (v & 0x1ffff) << 0; | 127 | return (v & 0x3ffff) << 0; |
128 | } | 128 | } |
129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | 129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) |
130 | { | 130 | { |
@@ -132,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | |||
132 | } | 132 | } |
133 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | 133 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) |
134 | { | 134 | { |
135 | return (v & 0x1ffff) << 0; | 135 | return (v & 0x3ffff) << 0; |
136 | } | 136 | } |
137 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | 137 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) |
138 | { | 138 | { |