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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-30 18:18:11 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-13 22:18:35 -0400
commit1d9d7c04bbbaa38080c3c8f256546bd63f65d494 (patch)
treeeb130549cf93074b1d928f5cc7bd5f103678f091 /drivers/gpu/nvgpu/gp10b
parent72f6c441c80a2c697230400bf042e7b96bffca72 (diff)
gpu: nvgpu: Wait for empty always has GR enabled
Whenever wait for empty HAL is called, GR is out of reset. Check for GR being out of reset was adding an extra dependency to MC, so just remove that code. JIRA NVGPU-964 Change-Id: Ic6d607fd2e29359a67896973517d8de6542029e9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813522 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 2fb700f0..db6f5618 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -45,7 +45,6 @@
45#include <nvgpu/hw/gp10b/hw_gr_gp10b.h> 45#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
46#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> 46#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
47#include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h> 47#include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
48#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
49 48
50#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000 49#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000
51 50
@@ -1452,7 +1451,6 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1452 u32 expect_delay) 1451 u32 expect_delay)
1453{ 1452{
1454 u32 delay = expect_delay; 1453 u32 delay = expect_delay;
1455 bool gr_enabled;
1456 bool ctxsw_active; 1454 bool ctxsw_active;
1457 bool gr_busy; 1455 bool gr_busy;
1458 u32 gr_status; 1456 u32 gr_status;
@@ -1468,9 +1466,6 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1468 only when gr_status is read */ 1466 only when gr_status is read */
1469 gr_status = gk20a_readl(g, gr_status_r()); 1467 gr_status = gk20a_readl(g, gr_status_r());
1470 1468
1471 gr_enabled = gk20a_readl(g, mc_enable_r()) &
1472 mc_enable_pgraph_enabled_f();
1473
1474 ctxsw_active = gr_status & 1<<7; 1469 ctxsw_active = gr_status & 1<<7;
1475 1470
1476 activity0 = gk20a_readl(g, gr_activity_0_r()); 1471 activity0 = gk20a_readl(g, gr_activity_0_r());
@@ -1483,7 +1478,7 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1483 activity2 == 0 && 1478 activity2 == 0 &&
1484 gr_activity_empty_or_preempted(activity4)); 1479 gr_activity_empty_or_preempted(activity4));
1485 1480
1486 if (!gr_enabled || (!gr_busy && !ctxsw_active)) { 1481 if (!gr_busy && !ctxsw_active) {
1487 nvgpu_log_fn(g, "done"); 1482 nvgpu_log_fn(g, "done");
1488 return 0; 1483 return 0;
1489 } 1484 }