diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 19:43:31 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:07:00 -0400 |
commit | 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 (patch) | |
tree | f2f2c234e20f8a7ff863b7da0bc3726ec306f4fe /drivers/gpu/nvgpu/gp10b | |
parent | 29b688960fcf6279f58d95f7e17f31ef15129a80 (diff) |
gpu: nvgpu: add resume_single_sm gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index afd3750b..a1be22df 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1860,7 +1860,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1860 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1860 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1861 | "CILP: resume for gpc %d tpc %d\n", | 1861 | "CILP: resume for gpc %d tpc %d\n", |
1862 | gpc, tpc); | 1862 | gpc, tpc); |
1863 | gk20a_resume_single_sm(g, gpc, tpc); | 1863 | g->ops.gr.resume_single_sm(g, gpc, tpc, sm); |
1864 | 1864 | ||
1865 | *ignore_debugger = true; | 1865 | *ignore_debugger = true; |
1866 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); | 1866 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); |