gpu: nvgpu: re-arrange parity counters

(1) Re-arrange the structure for parity counters reporting so multiple
units can be managed

JIRA: GPUT19X-84

Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485276
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 56 insertions, 42 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
new file mode 100644
index 00000000..454dcb20
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
@@ -0,0 +1,41 @@
+/*
+ * GP10B ECC
+ *
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_ECC_GP10B_H_
+#define _NVGPU_ECC_GP10B_H_
+
+#include <linux/version.h>
+
+struct ecc_gr_t18x {
+        struct gk20a_ecc_stat sm_lrf_single_err_count;
+        struct gk20a_ecc_stat sm_lrf_double_err_count;
+
+        struct gk20a_ecc_stat sm_shm_sec_count;
+        struct gk20a_ecc_stat sm_shm_sed_count;
+        struct gk20a_ecc_stat sm_shm_ded_count;
+
+        struct gk20a_ecc_stat tex_total_sec_pipe0_count;
+        struct gk20a_ecc_stat tex_total_ded_pipe0_count;
+        struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
+        struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
+        struct gk20a_ecc_stat tex_total_sec_pipe1_count;
+        struct gk20a_ecc_stat tex_total_ded_pipe1_count;
+        struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
+        struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
+
+        struct gk20a_ecc_stat l2_sec_count;
+        struct gk20a_ecc_stat l2_ded_count;
+};
+#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1853aaec..2c85a667 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -169,7 +169,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                                                 lrf_ecc_ded_status,
                                                 &lrf_single_count_delta,
                                                 lrf_double_count_delta);
-                g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] +=
+                g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] +=
                                                         lrf_single_count_delta;
         }
         if (lrf_ecc_ded_status) {
@@ -181,7 +181,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                                                 lrf_ecc_ded_status,
                                                 &lrf_double_count_delta,
                                                 lrf_single_count_delta);
-                g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] +=
+                g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] +=
                                                         lrf_double_count_delta;
         }
         gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
@@ -206,9 +206,9 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 ecc_stats_reg_val =
                         gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
-                g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] +=
+                g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
-                g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] +=
+                g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
                                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
@@ -228,7 +228,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 ecc_stats_reg_val =
                         gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
-                g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] +=
+                g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] +=
                         gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
                 gk20a_writel(g,
@@ -269,7 +269,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
                 gk20a_writel(g,
@@ -278,7 +278,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
                 gk20a_writel(g,
@@ -293,7 +293,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
                 gk20a_writel(g,
@@ -302,7 +302,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
                 gk20a_writel(g,
@@ -325,7 +325,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
                 gk20a_writel(g,
@@ -334,7 +334,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
                 gk20a_writel(g,
@@ -349,7 +349,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
-                g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
                 gk20a_writel(g,
@@ -358,7 +358,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 ecc_stats_reg_val = gk20a_readl(g,
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
-                g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] +=
+                g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] +=
                                 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
                 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
                 gk20a_writel(g,
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 588a7d8f..81ec7927 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -22,12 +22,6 @@
 
 struct gpu_ops;
 
-struct gr_gp10b_ecc_stat {
-        char **names;
-        u32 *counters;
-        struct hlist_node hash_node;
-};
-
 enum {
         PASCAL_CHANNEL_GPFIFO_A  = 0xC06F,
         PASCAL_A                 = 0xC097,
@@ -68,27 +62,6 @@ struct gr_t18x {
                 struct dentry *debugfs_dump_ctxsw_stats;
         } ctx_vars;
 
-        struct {
-                struct gr_gp10b_ecc_stat sm_lrf_single_err_count;
-                struct gr_gp10b_ecc_stat sm_lrf_double_err_count;
-
-                struct gr_gp10b_ecc_stat sm_shm_sec_count;
-                struct gr_gp10b_ecc_stat sm_shm_sed_count;
-                struct gr_gp10b_ecc_stat sm_shm_ded_count;
-
-                struct gr_gp10b_ecc_stat tex_total_sec_pipe0_count;
-                struct gr_gp10b_ecc_stat tex_total_ded_pipe0_count;
-                struct gr_gp10b_ecc_stat tex_unique_sec_pipe0_count;
-                struct gr_gp10b_ecc_stat tex_unique_ded_pipe0_count;
-                struct gr_gp10b_ecc_stat tex_total_sec_pipe1_count;
-                struct gr_gp10b_ecc_stat tex_total_ded_pipe1_count;
-                struct gr_gp10b_ecc_stat tex_unique_sec_pipe1_count;
-                struct gr_gp10b_ecc_stat tex_unique_ded_pipe1_count;
-
-                struct gr_gp10b_ecc_stat l2_sec_count;
-                struct gr_gp10b_ecc_stat l2_ded_count;
-        } ecc_stats;
-
         u32 fecs_feature_override_ecc_val;
 
         int cilp_preempt_pending_chid;
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index e65e3d06..165e93fe 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -149,7 +149,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
                                 ecc_stats_reg_val =
                                         gk20a_readl(g,
                                                 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
-                                g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] +=
+                                g->ecc.gr.t18x.l2_sec_count.counters[ltc] +=
                                         ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
                                 ecc_stats_reg_val &=
                                         ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
@@ -169,7 +169,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
                                 ecc_stats_reg_val =
                                         gk20a_readl(g,
                                                 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
-                                g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] +=
+                                g->ecc.gr.t18x.l2_ded_count.counters[ltc] +=
                                         ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
                                 ecc_stats_reg_val &=
                                         ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());