gpu: nvgpu: Add multiple engine and runlist support

This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
   Pascal GPU series
5) Removed hard coded engine_id logic and
   made generic way
6) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
index 5763b3b1..63efc945 100644
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
@@ -82,13 +82,16 @@ static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
 {
         u32 gate_ctrl;
         u32 engine_id;
+        u32 active_engine_id = 0;
+        struct fifo_gk20a *f = &g->fifo;
 
-        for (engine_id = 0; engine_id < ENGINE_INVAL_GK20A; engine_id++) {
-                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine_id));
+        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+                active_engine_id = f->active_engines_list[engine_id];
+                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
                 gate_ctrl = set_field(gate_ctrl,
                         therm_gate_ctrl_eng_delay_before_m(),
                         therm_gate_ctrl_eng_delay_before_f(4));
-                gk20a_writel(g, therm_gate_ctrl_r(engine_id), gate_ctrl);
+                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
         }
 
         return 0;