gpu: nvgpu: gp10b: add delay cycles before elcg

Update prod value for gr engine delay cycles before
engine clock gating. For copy engine, it was updated
earlier and now it is extended to both gr and ce.

Bug 1689806

Change-Id: I457ad6f9c461db89d53c57e68ad937ab5292849e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1129922
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 9 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
index 687593b0..5763b3b1 100644
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
@@ -81,12 +81,15 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g)
 static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
 {
         u32 gate_ctrl;
-
-        gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A));
-        gate_ctrl = set_field(gate_ctrl,
-                therm_gate_ctrl_eng_delay_before_m(),
-                therm_gate_ctrl_eng_delay_before_f(4));
-        gk20a_writel(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A), gate_ctrl);
+        u32 engine_id;
+
+        for (engine_id = 0; engine_id < ENGINE_INVAL_GK20A; engine_id++) {
+                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine_id));
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_delay_before_m(),
+                        therm_gate_ctrl_eng_delay_before_f(4));
+                gk20a_writel(g, therm_gate_ctrl_r(engine_id), gate_ctrl);
+        }
 
         return 0;
 }