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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-03 15:54:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 01:42:09 -0400
commit6d8d5eb17796bcd70d172f196adbca3bd1b964c4 (patch)
tree6ec7263105e9f6df032406a65afeb54080f87f4a /drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
parent59f07dcdc5480bd233d7e74ad733dc1f85d0b374 (diff)
gpu: nvgpu: Remove Pascal replayable fault support
We do not utilize or test replayable page faults in Pascal. Remove the code related to that. JIRA NVGPU-714 Change-Id: I2415bde347f8b018ebf99c3f9038d47c649d9464 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c158
1 files changed, 0 insertions, 158 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
deleted file mode 100644
index 7a714441..00000000
--- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * GP10B RPFB
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/dma.h>
26
27#include "gk20a/gk20a.h"
28
29#include "rpfb_gp10b.h"
30
31#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
32#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
33#include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
34
35int gp10b_replayable_pagefault_buffer_init(struct gk20a *g)
36{
37 u32 addr_lo;
38 u32 addr_hi;
39 struct vm_gk20a *vm = g->mm.bar2.vm;
40 int err;
41 size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE *
42 fifo_replay_fault_buffer_size_hw_entries_v();
43
44 nvgpu_log_fn(g, " ");
45
46 if (!g->mm.bar2_desc.gpu_va) {
47 err = nvgpu_dma_alloc_map_sys(vm, rbfb_size,
48 &g->mm.bar2_desc);
49 if (err) {
50 nvgpu_err(g, "Error in replayable fault buffer");
51 return err;
52 }
53 }
54 addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12);
55 addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va);
56 gk20a_writel(g, fifo_replay_fault_buffer_hi_r(),
57 fifo_replay_fault_buffer_hi_base_f(addr_hi));
58
59 gk20a_writel(g, fifo_replay_fault_buffer_lo_r(),
60 fifo_replay_fault_buffer_lo_base_f(addr_lo) |
61 fifo_replay_fault_buffer_lo_enable_true_v());
62 nvgpu_log_fn(g, "done");
63 return 0;
64}
65
66void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g)
67{
68 struct vm_gk20a *vm = g->mm.bar2.vm;
69
70 nvgpu_dma_unmap_free(vm, &g->mm.bar2_desc);
71}
72
73u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g)
74{
75 u32 get_idx = 0;
76
77 nvgpu_log_fn(g, " ");
78
79 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
80
81 if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
82 nvgpu_err(g, "Error in replayable fault buffer");
83
84 nvgpu_log_fn(g, "done");
85 return get_idx;
86}
87
88u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g)
89{
90 u32 put_idx = 0;
91
92 nvgpu_log_fn(g, " ");
93 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
94
95 if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
96 nvgpu_err(g, "Error in UVM");
97
98 nvgpu_log_fn(g, "done");
99 return put_idx;
100}
101
102bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g)
103{
104 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
105 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
106
107 return (get_idx == put_idx ? true : false);
108}
109
110bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g)
111{
112 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
113 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
114 u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r());
115
116 return (get_idx == ((put_idx + 1) % hw_entries) ? true : false);
117}
118
119bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g)
120{
121 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
122
123 return fifo_replay_fault_buffer_info_overflow_f(info);
124}
125
126void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g)
127{
128 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
129
130 info |= fifo_replay_fault_buffer_info_overflow_clear_v();
131 gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info);
132
133}
134
135/*
136 * Debug function.
137 */
138void gp10b_replayable_pagefault_buffer_info(struct gk20a *g)
139{
140 nvgpu_info(g, "rpfb low: 0x%x\n",
141 gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12);
142 nvgpu_info(g, "rpfb hi: 0x%x\n",
143 gk20a_readl(g, fifo_replay_fault_buffer_hi_r()));
144 nvgpu_info(g, "rpfb enabled: 0x%x\n",
145 gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1);
146 nvgpu_info(g, "rpfb size: %d\n",
147 gk20a_readl(g, fifo_replay_fault_buffer_size_r()));
148 nvgpu_info(g, "rpfb get index: %d\n",
149 gp10b_replayable_pagefault_buffer_get_index(g));
150 nvgpu_info(g, "rpfb put index: %d\n",
151 gp10b_replayable_pagefault_buffer_put_index(g));
152 nvgpu_info(g, "rpfb empty: %d\n",
153 gp10b_replayable_pagefault_buffer_is_empty(g));
154 nvgpu_info(g, "rpfb full %d\n",
155 gp10b_replayable_pagefault_buffer_is_full(g));
156 nvgpu_info(g, "rpfb overflow %d\n",
157 gp10b_replayable_pagefault_buffer_is_overflow(g));
158}
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