diff options
author | Philip Elcan <pelcan@nvidia.com> | 2018-08-23 14:45:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:47:25 -0400 |
commit | 2d0149c9abd74fd6bb59e076cfd46f49097e5662 (patch) | |
tree | 3d14929f7721440b777abfc150a35abbb1b03f36 /drivers/gpu/nvgpu/gp10b/regops_gp10b.h | |
parent | 74639b444251d7adc222400625eb59a3d53d0c0a (diff) |
gpu: nvgpu: resolve MISRA 10.3 violations
MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.
This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.
JIRA NVGPU-647
Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/regops_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h index 7bc08189..e8b9f325 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GP10B GPU Debugger Driver Register Ops | 3 | * Tegra GP10B GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,17 +28,17 @@ | |||
28 | struct dbg_session_gk20a; | 28 | struct dbg_session_gk20a; |
29 | 29 | ||
30 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void); | 30 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void); |
31 | int gp10b_get_global_whitelist_ranges_count(void); | 31 | u64 gp10b_get_global_whitelist_ranges_count(void); |
32 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void); | 32 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void); |
33 | int gp10b_get_context_whitelist_ranges_count(void); | 33 | u64 gp10b_get_context_whitelist_ranges_count(void); |
34 | const u32 *gp10b_get_runcontrol_whitelist(void); | 34 | const u32 *gp10b_get_runcontrol_whitelist(void); |
35 | int gp10b_get_runcontrol_whitelist_count(void); | 35 | u64 gp10b_get_runcontrol_whitelist_count(void); |
36 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void); | 36 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void); |
37 | int gp10b_get_runcontrol_whitelist_ranges_count(void); | 37 | u64 gp10b_get_runcontrol_whitelist_ranges_count(void); |
38 | const u32 *gp10b_get_qctl_whitelist(void); | 38 | const u32 *gp10b_get_qctl_whitelist(void); |
39 | int gp10b_get_qctl_whitelist_count(void); | 39 | u64 gp10b_get_qctl_whitelist_count(void); |
40 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void); | 40 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void); |
41 | int gp10b_get_qctl_whitelist_ranges_count(void); | 41 | u64 gp10b_get_qctl_whitelist_ranges_count(void); |
42 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 42 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
43 | 43 | ||
44 | #endif /* __REGOPS_GP10B_H_ */ | 44 | #endif /* __REGOPS_GP10B_H_ */ |