diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-09-04 07:07:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-05 23:41:36 -0400 |
commit | 2998ab4e0a0b19da1332b82d779bd17b4e284b38 (patch) | |
tree | e86e3201c1920f8cb0afecdb6e21f9c0bf8de366 /drivers/gpu/nvgpu/gp10b/regops_gp10b.c | |
parent | 2b2bde04e14135cae5f7433c755e6b8d70f88abb (diff) |
gpu: nvgpu: remove unused regops HALs
Below regops HALs are not being called from anywhere, so remove them
gops.regops.get_runcontrol_whitelist_ranges()
gops.regops.get_runcontrol_whitelist_ranges_count()
gops.regops.get_qctl_whitelist_ranges()
gops.regops.get_qctl_whitelist_ranges_count()
HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it
was originally only needed for gk20a which is not unsupported
So remove this HAL and its call too
Jira NVGPU-620
Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/regops_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 8113f7d5..c61709e0 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c | |||
@@ -23,12 +23,9 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gp10b.h" | 27 | #include "regops_gp10b.h" |
29 | 28 | ||
30 | #include <nvgpu/bsearch.h> | ||
31 | |||
32 | static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { | 29 | static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { |
33 | { 0x000004f0, 1}, | 30 | { 0x000004f0, 1}, |
34 | { 0x00001a00, 3}, | 31 | { 0x00001a00, 3}, |
@@ -393,23 +390,12 @@ static const u32 gp10b_runcontrol_whitelist[] = { | |||
393 | static const u64 gp10b_runcontrol_whitelist_count = | 390 | static const u64 gp10b_runcontrol_whitelist_count = |
394 | ARRAY_SIZE(gp10b_runcontrol_whitelist); | 391 | ARRAY_SIZE(gp10b_runcontrol_whitelist); |
395 | 392 | ||
396 | static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { | ||
397 | }; | ||
398 | static const u64 gp10b_runcontrol_whitelist_ranges_count = | ||
399 | ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); | ||
400 | |||
401 | |||
402 | /* quad ctl */ | 393 | /* quad ctl */ |
403 | static const u32 gp10b_qctl_whitelist[] = { | 394 | static const u32 gp10b_qctl_whitelist[] = { |
404 | }; | 395 | }; |
405 | static const u64 gp10b_qctl_whitelist_count = | 396 | static const u64 gp10b_qctl_whitelist_count = |
406 | ARRAY_SIZE(gp10b_qctl_whitelist); | 397 | ARRAY_SIZE(gp10b_qctl_whitelist); |
407 | 398 | ||
408 | static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { | ||
409 | }; | ||
410 | static const u64 gp10b_qctl_whitelist_ranges_count = | ||
411 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); | ||
412 | |||
413 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) | 399 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) |
414 | { | 400 | { |
415 | return gp10b_global_whitelist_ranges; | 401 | return gp10b_global_whitelist_ranges; |
@@ -440,16 +426,6 @@ u64 gp10b_get_runcontrol_whitelist_count(void) | |||
440 | return gp10b_runcontrol_whitelist_count; | 426 | return gp10b_runcontrol_whitelist_count; |
441 | } | 427 | } |
442 | 428 | ||
443 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) | ||
444 | { | ||
445 | return gp10b_runcontrol_whitelist_ranges; | ||
446 | } | ||
447 | |||
448 | u64 gp10b_get_runcontrol_whitelist_ranges_count(void) | ||
449 | { | ||
450 | return gp10b_runcontrol_whitelist_ranges_count; | ||
451 | } | ||
452 | |||
453 | const u32 *gp10b_get_qctl_whitelist(void) | 429 | const u32 *gp10b_get_qctl_whitelist(void) |
454 | { | 430 | { |
455 | return gp10b_qctl_whitelist; | 431 | return gp10b_qctl_whitelist; |
@@ -459,19 +435,3 @@ u64 gp10b_get_qctl_whitelist_count(void) | |||
459 | { | 435 | { |
460 | return gp10b_qctl_whitelist_count; | 436 | return gp10b_qctl_whitelist_count; |
461 | } | 437 | } |
462 | |||
463 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) | ||
464 | { | ||
465 | return gp10b_qctl_whitelist_ranges; | ||
466 | } | ||
467 | |||
468 | u64 gp10b_get_qctl_whitelist_ranges_count(void) | ||
469 | { | ||
470 | return gp10b_qctl_whitelist_ranges_count; | ||
471 | } | ||
472 | |||
473 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
474 | { | ||
475 | /* Not needed on gp10b */ | ||
476 | return 0; | ||
477 | } | ||