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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-10 11:28:23 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-13 17:06:17 -0400
commite62785190f74cfbf9003a190a768e9077373bf6f (patch)
treebe7bf93828c948d3b9bc84ec31f3f21cec35cf9e /drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
parent0706e94c9204becdee6a32391a319cad690d1bc3 (diff)
gpu: nvgpu: Move priv_ring HAL to common
Move implementation of priv_ring HAL to common/priv_ring. Implement two new HAL APIs to remove illegal dependencies: enable_priv_ring and enum_ltc. As enum_ltc can be implemented only gm20b onwards, bump gk20a implementation to base on gm20b. JIRA NVGPU-964 Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797025 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c199
1 files changed, 0 insertions, 199 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
deleted file mode 100644
index 9fcf060b..00000000
--- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * GP10B priv ring
3 *
4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26
27#include <nvgpu/log.h>
28#include <nvgpu/timers.h>
29#include <nvgpu/enabled.h>
30#include <nvgpu/io.h>
31#include <nvgpu/utils.h>
32
33#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
34#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h>
35#include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h>
36#include <nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h>
37
38#include "priv_ring_gp10b.h"
39
40static const char *const error_type_badf1xyy[] = {
41 "client timeout",
42 "decode error",
43 "client in reset",
44 "client floorswept",
45 "client stuck ack",
46 "client expected ack",
47 "fence error",
48 "subid error",
49 "byte access unsupported",
50};
51
52static const char *const error_type_badf2xyy[] = {
53 "orphan gpc/fbp"
54};
55
56static const char *const error_type_badf3xyy[] = {
57 "priv ring dead"
58};
59
60static const char *const error_type_badf5xyy[] = {
61 "client error",
62 "priv level violation",
63 "indirect priv level violation",
64 "local local ring error",
65 "falcon mem access priv level violation",
66 "pri route error"
67};
68
69void gp10b_priv_ring_decode_error_code(struct gk20a *g,
70 u32 error_code)
71{
72 u32 error_type_index;
73
74 error_type_index = (error_code & 0x00000f00) >> 16;
75 error_code = error_code & 0xBADFf000;
76
77 if (error_code == 0xBADF1000) {
78 if (error_type_index <
79 ARRAY_SIZE(error_type_badf1xyy))
80 nvgpu_err(g, "%s",
81 error_type_badf1xyy[error_type_index]);
82 } else if (error_code == 0xBADF2000) {
83 if (error_type_index <
84 ARRAY_SIZE(error_type_badf2xyy))
85 nvgpu_err(g, "%s",
86 error_type_badf2xyy[error_type_index]);
87 } else if (error_code == 0xBADF3000) {
88 if (error_type_index <
89 ARRAY_SIZE(error_type_badf3xyy))
90 nvgpu_err(g, "%s",
91 error_type_badf3xyy[error_type_index]);
92 } else if (error_code == 0xBADF5000) {
93 if (error_type_index <
94 ARRAY_SIZE(error_type_badf5xyy))
95 nvgpu_err(g, "%s",
96 error_type_badf5xyy[error_type_index]);
97 }
98}
99
100void gp10b_priv_ring_isr(struct gk20a *g)
101{
102 u32 status0, status1;
103 u32 cmd;
104 s32 retry = 100;
105 u32 gpc;
106 u32 gpc_stride, offset;
107 u32 error_info;
108 u32 error_code;
109
110 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
111 nvgpu_info(g, "unhandled priv ring intr");
112 return;
113 }
114
115 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
116 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
117
118 nvgpu_err(g, "ringmaster intr status0: 0x%08x,"
119 "status1: 0x%08x", status0, status1);
120
121 if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0)
122 nvgpu_err(g,
123 "BUG: connectivity problem on the startup sequence");
124
125 if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0)
126 nvgpu_err(g, "ring disconnected");
127
128 if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0)
129 nvgpu_err(g, "ring overflowed");
130
131 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
132 error_info =
133 gk20a_readl(g, pri_ringstation_sys_priv_error_info_r());
134 error_code =
135 gk20a_readl(g, pri_ringstation_sys_priv_error_code_r());
136 nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x "
137 "INFO 0x%08x (subid 0x%08x priv level %d), "
138 "CODE 0x%08x",
139 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
140 gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
141 error_info,
142 pri_ringstation_sys_priv_error_info_subid_v(error_info),
143 pri_ringstation_sys_priv_error_info_priv_level_v(error_info),
144 error_code);
145 if (g->ops.priv_ring.decode_error_code)
146 g->ops.priv_ring.decode_error_code(g, error_code);
147 }
148
149 if (status1) {
150 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
151 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
152 offset = gpc * gpc_stride;
153 if (status1 & BIT(gpc)) {
154 error_info = gk20a_readl(g,
155 pri_ringstation_gpc_gpc0_priv_error_info_r() + offset);
156 error_code = gk20a_readl(g,
157 pri_ringstation_gpc_gpc0_priv_error_code_r() + offset);
158 nvgpu_err(g, "GPC%u write error. ADR 0x%08x "
159 "WRDAT 0x%08x "
160 "INFO 0x%08x (subid 0x%08x priv level %d), "
161 "CODE 0x%08x", gpc,
162 gk20a_readl(g,
163 pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset),
164 gk20a_readl(g,
165 pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset),
166 error_info,
167 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info),
168 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info),
169 error_code);
170
171 if (g->ops.priv_ring.decode_error_code)
172 g->ops.priv_ring.decode_error_code(g,
173 error_code);
174
175 status1 = status1 & (~(BIT(gpc)));
176 if (!status1)
177 break;
178 }
179 }
180 }
181 /* clear interrupt */
182 cmd = gk20a_readl(g, pri_ringmaster_command_r());
183 cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
184 pri_ringmaster_command_cmd_ack_interrupt_f());
185 gk20a_writel(g, pri_ringmaster_command_r(), cmd);
186
187 /* poll for clear interrupt done */
188 cmd = pri_ringmaster_command_cmd_v(
189 gk20a_readl(g, pri_ringmaster_command_r()));
190 while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) {
191 nvgpu_udelay(20);
192 cmd = pri_ringmaster_command_cmd_v(
193 gk20a_readl(g, pri_ringmaster_command_r()));
194 retry--;
195 }
196
197 if (retry == 0)
198 nvgpu_err(g, "priv ringmaster intr ack failed");
199}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:37:21 -0400