gpu: nvgpu: Introduce priv ring HAL and define ISR

Introduce a priv ring HAL and define ISR as the only function in it.
Introduce a gp10b version of the ISR that writes error message to
UART for every priv ring error, and leave the old chips with silent
error handling.

Bug 1846641

Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473696
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 82 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
new file mode 100644
index 00000000..7cdbec5e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
@@ -0,0 +1,82 @@
+/*
+ * GP10B priv ring
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+
+#include <nvgpu/log.h>
+#include <nvgpu/timers.h>
+
+#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h>
+
+static void gp10b_priv_ring_isr(struct gk20a *g)
+{
+        u32 status0, status1;
+        u32 cmd;
+        s32 retry = 100;
+        u32 gpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+
+        if (g->is_fmodel)
+                return;
+
+        status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
+        status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
+
+        nvgpu_err(g, "ringmaster intr status0: 0x%08x,"
+                "status1: 0x%08x", status0, status1);
+
+        if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
+                nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
+        }
+
+        for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
+                if (status1 & BIT(gpc)) {
+                        nvgpu_err(g, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
+                }
+        }
+
+        cmd = gk20a_readl(g, pri_ringmaster_command_r());
+        cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
+                pri_ringmaster_command_cmd_ack_interrupt_f());
+        gk20a_writel(g, pri_ringmaster_command_r(), cmd);
+
+        do {
+                cmd = pri_ringmaster_command_cmd_v(
+                        gk20a_readl(g, pri_ringmaster_command_r()));
+                nvgpu_usleep_range(20, 40);
+        } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry);
+
+        if (retry <= 0)
+                nvgpu_warn(g, "priv ringmaster cmd ack too many retries");
+}
+
+void gp10b_init_priv_ring(struct gpu_ops *gops)
+{
+        gops->priv_ring.isr = gp10b_priv_ring_isr;
+}