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| author | Vijayakumar <vsubbu@nvidia.com> | 2016-11-07 07:42:19 -0500 |
|---|---|---|
| committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:52 -0500 |
| commit | f7290e6a83282ed96b4af225d7d7b63230138d7c (patch) | |
| tree | 7aa41034d933b4ee34fe6dd39355e8fd21977561 /drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |
| parent | 8edfc9ee67d8c346310b2ad653754440719a29d7 (diff) | |
gpu: nvgpu: fix fll regime check
For target clocks >= FFR cutoff clock use FR, else use FFR.
JIRA DNVGPU-180
Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1249041
(cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11)
Reviewed-on: http://git-master/r/1270883
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
0 files changed, 0 insertions, 0 deletions