gpu: nvgpu: rename gk20a_pmu_cmd_post()

- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
  wherever called.

JIRA NVGPU-93

Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index b086bf1f..dbaf3ebf 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -166,7 +166,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
                                 u64_hi32(g->pmu.wpr_buf.gpu_va);
                 gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
                                 falconidmask);
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
         }
 
@@ -242,7 +242,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
                                 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
 
                 gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM ");
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_gr_param_msg, pmu, &seq, ~0);
 
         } else