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authorSunny He <suhe@nvidia.com>2017-08-01 18:03:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-21 16:06:04 -0400
commitb50b379c192714d0d08c3f2d33e90c95cf795253 (patch)
treebd7786d1fec51f168a9393fcb16a8fe56ad25044 /drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
parent192f1039e11893b9216819837eee871612225849 (diff)
gpu: nvgpu: Move non-fp pmu members from gpu_ops
Move non-function pointer members out of the pmu and pmu_ver substructs of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to g.pmu_ver_cmd_id_zbc_table_update - g.ops.pmu.lspmuwprinitdone has been changed to g.pmu_lsf_pmu_wpr_init_done - g.ops.pmu.lsfloadedfalconid has been changed to g.pmu_lsf_loaded_falcon_id Boolean flags have been implemented using the enabled.h API - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to common flag NVGPU_PMU_ZBC_SAVE - g.ops.pmu.fecsbootstrapdone moved to common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE Jira NVGPU-74 Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530981 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index da8044cd..f45490db 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -148,8 +148,8 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
148 148
149 gk20a_dbg_fn(""); 149 gk20a_dbg_fn("");
150 150
151 gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); 151 gp10b_dbg_pmu("wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done);
152 if (g->ops.pmu.lspmuwprinitdone) { 152 if (g->pmu_lsf_pmu_wpr_init_done) {
153 /* send message to load FECS falcon */ 153 /* send message to load FECS falcon */
154 memset(&cmd, 0, sizeof(struct pmu_cmd)); 154 memset(&cmd, 0, sizeof(struct pmu_cmd));
155 cmd.hdr.unit_id = PMU_UNIT_ACR; 155 cmd.hdr.unit_id = PMU_UNIT_ACR;
@@ -185,14 +185,14 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
185 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | 185 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
186 (1 << LSF_FALCON_ID_GPCCS))) 186 (1 << LSF_FALCON_ID_GPCCS)))
187 return -EINVAL; 187 return -EINVAL;
188 g->ops.pmu.lsfloadedfalconid = 0; 188 g->pmu_lsf_loaded_falcon_id = 0;
189 /* check whether pmu is ready to bootstrap lsf if not wait for it */ 189 /* check whether pmu is ready to bootstrap lsf if not wait for it */
190 if (!g->ops.pmu.lspmuwprinitdone) { 190 if (!g->pmu_lsf_pmu_wpr_init_done) {
191 pmu_wait_message_cond(&g->pmu, 191 pmu_wait_message_cond(&g->pmu,
192 gk20a_get_gr_idle_timeout(g), 192 gk20a_get_gr_idle_timeout(g),
193 &g->ops.pmu.lspmuwprinitdone, 1); 193 &g->pmu_lsf_pmu_wpr_init_done, 1);
194 /* check again if it still not ready indicate an error */ 194 /* check again if it still not ready indicate an error */
195 if (!g->ops.pmu.lspmuwprinitdone) { 195 if (!g->pmu_lsf_pmu_wpr_init_done) {
196 nvgpu_err(g, "PMU not ready to load LSF"); 196 nvgpu_err(g, "PMU not ready to load LSF");
197 return -ETIMEDOUT; 197 return -ETIMEDOUT;
198 } 198 }
@@ -201,8 +201,8 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
201 gp10b_pmu_load_multiple_falcons(g, falconidmask, flags); 201 gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
202 pmu_wait_message_cond(&g->pmu, 202 pmu_wait_message_cond(&g->pmu,
203 gk20a_get_gr_idle_timeout(g), 203 gk20a_get_gr_idle_timeout(g),
204 &g->ops.pmu.lsfloadedfalconid, falconidmask); 204 &g->pmu_lsf_loaded_falcon_id, falconidmask);
205 if (g->ops.pmu.lsfloadedfalconid != falconidmask) 205 if (g->pmu_lsf_loaded_falcon_id != falconidmask)
206 return -ETIMEDOUT; 206 return -ETIMEDOUT;
207 return 0; 207 return 0;
208} 208}
@@ -418,8 +418,8 @@ void gp10b_init_pmu_ops(struct gk20a *g)
418 gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; 418 gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v;
419 gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; 419 gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire;
420 gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; 420 gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release;
421 gops->pmu.lspmuwprinitdone = false; 421 g->pmu_lsf_pmu_wpr_init_done = false;
422 gops->pmu.fecsbootstrapdone = false; 422 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
423 gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; 423 gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
424 gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; 424 gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
425 gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; 425 gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init;