gpu: nvgpu: PMU init sequence change

-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
 method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
 for PMU RTOS & does start PMU RTOS in secure & non-secure
 based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
 falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
 secured_pmu_start assignment for gp106 & gv100 to support
 modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
 files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
 to handle non secure PMU bootstrap, reused this method
 for need chips.

JIRA NVGPU-1146

Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 39 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index 5c7d1523..d268ab88 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -304,45 +304,6 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
                                 0x0);
 }
 
-int gp10b_init_pmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-        if (err) {
-                return err;
-        }
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-
-}
-
 bool gp10b_is_lazy_bootstrap(u32 falcon_id)
 {
         bool enable_status = false;