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authorDeepak Nibade <dnibade@nvidia.com>2017-05-23 08:31:43 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-15 08:43:48 -0400
commit7d16f7e52c0f8ce8604e992a617a3f98545fcf07 (patch)
treee14b73435e847ddda77b4a72466b6aae44b9ff80 /drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
parenteb8db3e4df159210ca9c7f834dbbc939a5c67a96 (diff)
gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>
Remove <soc/tegra/fuse.h> includes and include <nvgpu/fuse.h> header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index cd6bf97a..2222cc17 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -13,10 +13,9 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <soc/tegra/fuse.h>
17
18#include <nvgpu/pmu.h> 16#include <nvgpu/pmu.h>
19#include <nvgpu/log.h> 17#include <nvgpu/log.h>
18#include <nvgpu/fuse.h>
20 19
21#include "gk20a/gk20a.h" 20#include "gk20a/gk20a.h"
22#include "gk20a/pmu_gk20a.h" 21#include "gk20a/pmu_gk20a.h"
@@ -383,7 +382,7 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
383 gk20a_readl(g, fuse_opt_sec_debug_en_r())); 382 gk20a_readl(g, fuse_opt_sec_debug_en_r()));
384 nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", 383 nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
385 gk20a_readl(g, fuse_opt_priv_sec_en_r())); 384 gk20a_readl(g, fuse_opt_priv_sec_en_r()));
386 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); 385 nvgpu_tegra_fuse_read_gcplex_config_fuse(&val);
387 nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", 386 nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
388 val); 387 val);
389} 388}