gpu: nvgpu: add platform atomic support

Add new variable in nvgpu_as_map_buffer_ex_args for app
to specify the platform atomic support for the page.
When platform atomic attribute flag is set, pte memory
aperture is set to be coherent type.

renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw
function.

bug 200580236

Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012679
(cherry picked from commit 9e0a9004b71f92b7713fd3b30141b0d9d4cfa2c6)
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274914
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Sreeniketh H <sh@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 31 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 2c0056e1..a4b291d8 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B MMU
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -78,6 +78,32 @@ clean_up_va:
         return err;
 }
 
+/*
+ * For GV11B and TU104 MSS NVLINK HW settings are in force_snoop mode.
+ * This will force all the GPU mappings to be coherent.
+ * By default the mem aperture sets as sysmem_non_coherent and will use L2 mode.
+ * Change target pte aperture to sysmem_coherent if mem attribute requests for
+ * platform atomics to use rmw atomic capability.
+ *
+ */
+static u32 gmmu_aperture_mask(struct gk20a *g,
+                                  enum nvgpu_aperture mem_ap,
+                                  bool platform_atomic_attr,
+                                  u32 sysmem_mask,
+                                  u32 sysmem_coh_mask,
+                                  u32 vidmem_mask)
+{
+        if (nvgpu_is_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC) &&
+                             platform_atomic_attr) {
+                mem_ap = APERTURE_SYSMEM_COH;
+        }
+
+        return nvgpu_aperture_mask_raw(g, mem_ap,
+                                sysmem_mask,
+                                sysmem_coh_mask,
+                                vidmem_mask);
+}
+
 static void update_gmmu_pde3_locked(struct vm_gk20a *vm,
                                     const struct gk20a_mmu_level *l,
                                     struct nvgpu_gmmu_pd *pd,
@@ -191,8 +217,9 @@ static void __update_pte(struct vm_gk20a *vm,
         u32 pte_addr = attrs->aperture == APERTURE_SYSMEM ?
                 gmmu_new_pte_address_sys_f(phys_shifted) :
                 gmmu_new_pte_address_vid_f(phys_shifted);
-        u32 pte_tgt = nvgpu_aperture_mask_coh(g,
+        u32 pte_tgt = gmmu_aperture_mask(g,
                                         attrs->aperture,
+                                        attrs->platform_atomic,
                                         gmmu_new_pte_aperture_sys_mem_ncoh_f(),
                                         gmmu_new_pte_aperture_sys_mem_coh_f(),
                                         gmmu_new_pte_aperture_video_memory_f());
@@ -253,7 +280,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
                 "vm=%s "
                 "PTE: i=%-4u size=%-2u | "
                 "GPU %#-12llx  phys %#-12llx "
-                "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c "
+                "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c%c "
                 "ctag=0x%08x "
                 "[0x%08x, 0x%08x]",
                 vm->name,
@@ -268,6 +295,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
                 attrs->priv      ? 'P' : '-',
                 attrs->coherent  ? 'I' : '-',
                 attrs->valid     ? 'V' : '-',
+                attrs->platform_atomic ? 'A' : '-',
                 (u32)attrs->ctag / g->ops.fb.compression_page_size(g),
                 pte_w[1], pte_w[0]);