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authorMatt Craighead <mcraighead@nvidia.com>2015-07-09 15:24:31 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:07 -0500
commitb0667dcd8ade3dd61ac3b32000ff6b25b077208d (patch)
tree94bfeba7552b3bb1f6a52331db358b0303648cc1 /drivers/gpu/nvgpu/gp10b/mm_gp10b.c
parentc965e6655800afffd3d4e3d73f28198adef7a118 (diff)
Revert "gpu: nvgpu: gp10b: Phys addresses for page tables"
This reverts commit f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5. Change-Id: I0acfa18e9cf9bedd4051ec00faa497b3cdb9454b Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/768599 Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 9f66c21f..190dc7f6 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -160,12 +160,13 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
160 struct gk20a_mm_entry *pte = parent->entries + i; 160 struct gk20a_mm_entry *pte = parent->entries + i;
161 u32 pde_v[2] = {0, 0}; 161 u32 pde_v[2] = {0, 0};
162 u32 *pde; 162 u32 *pde;
163 struct gk20a *g = vm->mm->g;
163 164
164 gk20a_dbg_fn(""); 165 gk20a_dbg_fn("");
165 166
166 pte_addr = virt_to_phys(pte->cpu_va) 167 pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0)
167 >> gmmu_new_pde_address_shift_v(); 168 >> gmmu_new_pde_address_shift_v();
168 pde_addr = virt_to_phys(parent->cpu_va); 169 pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0);
169 170
170 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); 171 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
171 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); 172 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
@@ -202,6 +203,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
202 struct gk20a_mm_entry *entry = pte->entries + i; 203 struct gk20a_mm_entry *entry = pte->entries + i;
203 u32 pde_v[4] = {0, 0, 0, 0}; 204 u32 pde_v[4] = {0, 0, 0, 0};
204 u32 *pde; 205 u32 *pde;
206 struct gk20a *g = vm->mm->g;
205 207
206 gk20a_dbg_fn(""); 208 gk20a_dbg_fn("");
207 209
@@ -209,11 +211,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
209 big_valid = entry->size && entry->pgsz == gmmu_page_size_big; 211 big_valid = entry->size && entry->pgsz == gmmu_page_size_big;
210 212
211 if (small_valid) 213 if (small_valid)
212 pte_addr_small = virt_to_phys(entry->cpu_va) 214 pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0)
213 >> gmmu_new_dual_pde_address_shift_v(); 215 >> gmmu_new_dual_pde_address_shift_v();
214 216
215 if (big_valid) 217 if (big_valid)
216 pte_addr_big = virt_to_phys(entry->cpu_va) 218 pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0)
217 >> gmmu_new_dual_pde_address_big_shift_v(); 219 >> gmmu_new_dual_pde_address_big_shift_v();
218 220
219 if (small_valid) { 221 if (small_valid) {