diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-08 15:03:32 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:12 -0500 |
commit | ae893b37c014b13f68aa7547640bda3589363f4d (patch) | |
tree | 5ac4fdb02df2513f0efc2f370d85521422888d4e /drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |
parent | 342d45e060ba9c6a7815633c351ec8d95422dcbb (diff) |
gpu: nvgpu: gp10b: Use sysmem aperture for SoC memory
In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it
has to be accessed as sysmem.
Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1122591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index deb8c138..0c00feb4 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -43,9 +43,11 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
43 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); | 43 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); |
44 | 44 | ||
45 | gk20a_writel(g, bus_bar1_block_r(), | 45 | gk20a_writel(g, bus_bar1_block_r(), |
46 | bus_bar1_block_target_vid_mem_f() | | 46 | (g->mm.vidmem_is_vidmem ? |
47 | bus_bar1_block_mode_virtual_f() | | 47 | bus_bar1_block_target_sys_mem_ncoh_f() : |
48 | bus_bar1_block_ptr_f(inst_pa)); | 48 | bus_bar1_block_target_vid_mem_f()) | |
49 | bus_bar1_block_mode_virtual_f() | | ||
50 | bus_bar1_block_ptr_f(inst_pa)); | ||
49 | 51 | ||
50 | if (g->ops.mm.init_bar2_mm_hw_setup) { | 52 | if (g->ops.mm.init_bar2_mm_hw_setup) { |
51 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 53 | err = g->ops.mm.init_bar2_mm_hw_setup(g); |
@@ -107,9 +109,11 @@ static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
107 | gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); | 109 | gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); |
108 | 110 | ||
109 | gk20a_writel(g, bus_bar2_block_r(), | 111 | gk20a_writel(g, bus_bar2_block_r(), |
110 | bus_bar2_block_target_vid_mem_f() | | 112 | (g->mm.vidmem_is_vidmem ? |
111 | bus_bar2_block_mode_virtual_f() | | 113 | bus_bar2_block_target_sys_mem_ncoh_f() : |
112 | bus_bar2_block_ptr_f(inst_pa)); | 114 | bus_bar2_block_target_vid_mem_f()) | |
115 | bus_bar2_block_mode_virtual_f() | | ||
116 | bus_bar2_block_ptr_f(inst_pa)); | ||
113 | 117 | ||
114 | gk20a_dbg_fn("done"); | 118 | gk20a_dbg_fn("done"); |
115 | return 0; | 119 | return 0; |
@@ -179,7 +183,9 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, | |||
179 | pte_addr = entry_addr(g, pte) >> gmmu_new_pde_address_shift_v(); | 183 | pte_addr = entry_addr(g, pte) >> gmmu_new_pde_address_shift_v(); |
180 | pde_addr = entry_addr(g, parent); | 184 | pde_addr = entry_addr(g, parent); |
181 | 185 | ||
182 | pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); | 186 | pde_v[0] |= g->mm.vidmem_is_vidmem ? |
187 | gmmu_new_pde_aperture_sys_mem_ncoh_f() : | ||
188 | gmmu_new_pde_aperture_video_memory_f(); | ||
183 | pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); | 189 | pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); |
184 | pde_v[0] |= gmmu_new_pde_vol_true_f(); | 190 | pde_v[0] |= gmmu_new_pde_vol_true_f(); |
185 | pde_v[1] |= pte_addr >> 24; | 191 | pde_v[1] |= pte_addr >> 24; |
@@ -232,7 +238,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, | |||
232 | 238 | ||
233 | if (small_valid) { | 239 | if (small_valid) { |
234 | pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); | 240 | pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); |
235 | pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f(); | 241 | pde_v[2] |= g->mm.vidmem_is_vidmem ? |
242 | gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() : | ||
243 | gmmu_new_dual_pde_aperture_small_video_memory_f(); | ||
236 | pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); | 244 | pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); |
237 | pde_v[3] |= pte_addr_small >> 24; | 245 | pde_v[3] |= pte_addr_small >> 24; |
238 | } | 246 | } |
@@ -240,7 +248,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, | |||
240 | if (big_valid) { | 248 | if (big_valid) { |
241 | pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); | 249 | pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); |
242 | pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); | 250 | pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); |
243 | pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f(); | 251 | pde_v[0] |= g->mm.vidmem_is_vidmem ? |
252 | gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() : | ||
253 | gmmu_new_dual_pde_aperture_big_video_memory_f(); | ||
244 | pde_v[1] |= pte_addr_big >> 28; | 254 | pde_v[1] |= pte_addr_big >> 28; |
245 | } | 255 | } |
246 | 256 | ||
@@ -279,8 +289,10 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, | |||
279 | pte_w[0] = gmmu_new_pte_valid_false_f(); | 289 | pte_w[0] = gmmu_new_pte_valid_false_f(); |
280 | else | 290 | else |
281 | pte_w[0] = gmmu_new_pte_valid_true_f(); | 291 | pte_w[0] = gmmu_new_pte_valid_true_f(); |
282 | pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() | | 292 | pte_w[0] |= g->mm.vidmem_is_vidmem ? |
283 | gmmu_new_pte_address_sys_f(*iova | 293 | gmmu_new_pte_aperture_sys_mem_ncoh_f() : |
294 | gmmu_new_pte_aperture_video_memory_f(); | ||
295 | pte_w[0] |= gmmu_new_pte_address_sys_f(*iova | ||
284 | >> gmmu_new_pte_address_shift_v()); | 296 | >> gmmu_new_pte_address_shift_v()); |
285 | 297 | ||
286 | if (priv) | 298 | if (priv) |
@@ -373,7 +385,9 @@ static void gp10b_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr) | |||
373 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 385 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
374 | 386 | ||
375 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), | 387 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), |
376 | ram_in_page_dir_base_target_vid_mem_f() | | 388 | (g->mm.vidmem_is_vidmem ? |
389 | ram_in_page_dir_base_target_sys_mem_ncoh_f() : | ||
390 | ram_in_page_dir_base_target_vid_mem_f()) | | ||
377 | ram_in_page_dir_base_vol_true_f() | | 391 | ram_in_page_dir_base_vol_true_f() | |
378 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | | 392 | ram_in_page_dir_base_lo_f(pdb_addr_lo) | |
379 | 1 << 10); | 393 | 1 << 10); |