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authorTerje Bergstrom <tbergstrom@nvidia.com>2015-08-10 17:53:47 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:07 -0500
commit8ae3f0ac28c3ee754ff7bbfe3f75b73e6ab33836 (patch)
treee588953916f45882d99a926084a6106029611fd3 /drivers/gpu/nvgpu/gp10b/mm_gp10b.c
parentb0667dcd8ade3dd61ac3b32000ff6b25b077208d (diff)
gpu: nvgpu: gp10b: Use phys addresses in PDEs
Use physical addresses in PDEs. All page table levels fit in 4k, so no need for SMMU mapping. Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/783748 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 190dc7f6..65449534 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -160,13 +160,11 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
160 struct gk20a_mm_entry *pte = parent->entries + i; 160 struct gk20a_mm_entry *pte = parent->entries + i;
161 u32 pde_v[2] = {0, 0}; 161 u32 pde_v[2] = {0, 0};
162 u32 *pde; 162 u32 *pde;
163 struct gk20a *g = vm->mm->g;
164 163
165 gk20a_dbg_fn(""); 164 gk20a_dbg_fn("");
166 165
167 pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0) 166 pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v();
168 >> gmmu_new_pde_address_shift_v(); 167 pde_addr = sg_phys(parent->sgt->sgl);
169 pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0);
170 168
171 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); 169 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
172 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); 170 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
@@ -203,7 +201,6 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
203 struct gk20a_mm_entry *entry = pte->entries + i; 201 struct gk20a_mm_entry *entry = pte->entries + i;
204 u32 pde_v[4] = {0, 0, 0, 0}; 202 u32 pde_v[4] = {0, 0, 0, 0};
205 u32 *pde; 203 u32 *pde;
206 struct gk20a *g = vm->mm->g;
207 204
208 gk20a_dbg_fn(""); 205 gk20a_dbg_fn("");
209 206
@@ -211,11 +208,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
211 big_valid = entry->size && entry->pgsz == gmmu_page_size_big; 208 big_valid = entry->size && entry->pgsz == gmmu_page_size_big;
212 209
213 if (small_valid) 210 if (small_valid)
214 pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) 211 pte_addr_small = sg_phys(entry->sgt->sgl)
215 >> gmmu_new_dual_pde_address_shift_v(); 212 >> gmmu_new_dual_pde_address_shift_v();
216 213
217 if (big_valid) 214 if (big_valid)
218 pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) 215 pte_addr_big = sg_phys(entry->sgt->sgl)
219 >> gmmu_new_dual_pde_address_big_shift_v(); 216 >> gmmu_new_dual_pde_address_big_shift_v();
220 217
221 if (small_valid) { 218 if (small_valid) {