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authorSeema Khowala <seemaj@nvidia.com>2018-01-17 15:09:38 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-18 17:38:57 -0500
commit872be3a4ac16f4d139a9597b3fdae4355cb4baf2 (patch)
tree2afb6b3deb5d1883e01a8c8f623c9c175f6383d0 /drivers/gpu/nvgpu/gp10b/mm_gp10b.c
parentf8402eb90a68ab1e38ef87166458dc064501a8f9 (diff)
gpu: nvgpu: ramin_big_page_size default val is set to 64kb
-MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is set to TRUE and hence RAMIN_BIG_PAGE_SIZE should be set to 64KB i.e. val 1. By default this is set to 128KB i.e. val 0. -This change will also fix an issue where perfbuffer_enable and nvgpu_init_hwpm function pass 0 as big page size while initializing inst_block and due to which ramin_big_page_size does not get updated to 64KB and remains set to unsupported 128KB value. -Volta supports 64KB for big pages. Selecting 128KB for big pages results in an UNBOUND_INSTANCE fault. Bug 200327596 Change-Id: Ie304e4e5ff7bedaead27e9380d64c59013dd64ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639540 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/mm_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 8cefbd3e..33591edc 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -431,8 +431,9 @@ void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
431 ram_in_page_dir_base_target_sys_mem_ncoh_f(), 431 ram_in_page_dir_base_target_sys_mem_ncoh_f(),
432 ram_in_page_dir_base_target_vid_mem_f()) | 432 ram_in_page_dir_base_target_vid_mem_f()) |
433 ram_in_page_dir_base_vol_true_f() | 433 ram_in_page_dir_base_vol_true_f() |
434 ram_in_big_page_size_64kb_f() |
434 ram_in_page_dir_base_lo_f(pdb_addr_lo) | 435 ram_in_page_dir_base_lo_f(pdb_addr_lo) |
435 1 << 10); 436 ram_in_use_ver2_pt_format_true_f());
436 437
437 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), 438 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
438 ram_in_page_dir_base_hi_f(pdb_addr_hi)); 439 ram_in_page_dir_base_hi_f(pdb_addr_hi));