gpu: nvgpu: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.

JIRA NVGPU-989

Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index a0e08437..7036ca15 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -286,8 +286,9 @@ static enum gmmu_pgsz_gk20a gp10b_get_pde0_pgsz(struct gk20a *g,
         if (!pd->mem)
                 return pgsz;
 
-        for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++)
+        for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) {
                 pde_v[i] = nvgpu_mem_rd32(g, pd->mem, pde_offset + i);
+        }
 
         /*
          * Check if the aperture AND address are set