gpu: nvgpu: Use correct PD for determining next aperture

When generating the aperture field for the PDE being programmed
we must use the next PD not the current PD. This is important for
cases on the dGPU where VIDMEM runs out.

In such cases the page table may reside in both VIDMEM and SYSMEM.
Thus, if a PDE points to a PDE in a different type of memory
(VIDMEM -> SYSMEM or SYSMEM -> VIDMEM) then the aperture will not
be programmed correctly if the code uses the current PD for
picking the next PD aperture.

Bug 2082475

Change-Id: Ic1a8d1e2c2237712039dc298b97095d3bbc6c844
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676831
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 86d5f5df..43d9fd28 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -143,12 +143,13 @@ static void update_gmmu_pde3_locked(struct vm_gk20a *vm,
                                     struct nvgpu_gmmu_attrs *attrs)
 {
         struct gk20a *g = gk20a_from_vm(vm);
+        struct nvgpu_gmmu_pd *next_pd = &pd->entries[pd_idx];
         u32 pd_offset = pd_offset_from_index(l, pd_idx);
         u32 pde_v[2] = {0, 0};
 
         phys_addr >>= gmmu_new_pde_address_shift_v();
 
-        pde_v[0] |= nvgpu_aperture_mask(g, pd->mem,
+        pde_v[0] |= nvgpu_aperture_mask(g, next_pd->mem,
                                         gmmu_new_pde_aperture_sys_mem_ncoh_f(),
                                         gmmu_new_pde_aperture_sys_mem_coh_f(),
                                         gmmu_new_pde_aperture_video_memory_f());
@@ -177,6 +178,7 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm,
                                     struct nvgpu_gmmu_attrs *attrs)
 {
         struct gk20a *g = gk20a_from_vm(vm);
+        struct nvgpu_gmmu_pd *next_pd = &pd->entries[pd_idx];
         bool small_valid, big_valid;
         u32 small_addr = 0, big_addr = 0;
         u32 pd_offset = pd_offset_from_index(l, pd_idx);
@@ -194,7 +196,7 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm,
         if (small_valid) {
                 pde_v[2] |=
                         gmmu_new_dual_pde_address_small_sys_f(small_addr);
-                pde_v[2] |= nvgpu_aperture_mask(g, pd->mem,
+                pde_v[2] |= nvgpu_aperture_mask(g, next_pd->mem,
                         gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(),
                         gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(),
                         gmmu_new_dual_pde_aperture_small_video_memory_f());
@@ -205,7 +207,7 @@ static void update_gmmu_pde0_locked(struct vm_gk20a *vm,
         if (big_valid) {
                 pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(big_addr);
                 pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
-                pde_v[0] |= nvgpu_aperture_mask(g, pd->mem,
+                pde_v[0] |= nvgpu_aperture_mask(g, next_pd->mem,
                         gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(),
                         gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(),
                         gmmu_new_dual_pde_aperture_big_video_memory_f());