gpu: nvgpu: gp10b: Program NISO sysmem flush addr

Program sysmem flush address to prevent random accesses of
address 0.

Change-Id: Ia577106c63a80589c154af41d18b70480ed7c7d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1149174
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

1 files changed, 5 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 0b693f7c..c25abc78 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -18,6 +18,7 @@
 #include "gk20a/gk20a.h"
 #include "mm_gp10b.h"
 #include "rpfb_gp10b.h"
+#include "hw_fb_gp10b.h"
 #include "hw_ram_gp10b.h"
 #include "hw_bus_gp10b.h"
 #include "hw_gmmu_gp10b.h"
@@ -39,15 +40,11 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g)
 
         g->ops.fb.set_mmu_page_size(g);
 
-        inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a());
-        gk20a_dbg_info("bar1 inst block ptr: 0x%08x",  (u32)inst_pa);
+        gk20a_writel(g, fb_niso_flush_sysmem_addr_r(),
+                     (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
+                     >> 8ULL));
 
-        gk20a_writel(g, bus_bar1_block_r(),
-                     (g->mm.vidmem_is_vidmem ?
-                       bus_bar1_block_target_sys_mem_ncoh_f() :
-                       bus_bar1_block_target_vid_mem_f()) |
-                     bus_bar1_block_mode_virtual_f() |
-                     bus_bar1_block_ptr_f(inst_pa));
+        g->ops.mm.bar1_bind(g, inst_pa);
 
         if (g->ops.mm.init_bar2_mm_hw_setup) {
                 err = g->ops.mm.init_bar2_mm_hw_setup(g);