gpu: nvgpu: Handle MC pmu interrupts

- Made changes to MC to get pmu interrrupts

Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/661212
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
index f274ce05..b2ec4be4 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
@@ -15,8 +15,15 @@
 #define MC_GP20B_H
 struct gk20a;
 
+enum MC_INTERRUPT_REGLIST {
+        NVGPU_MC_INTR_STALLING = 0,
+        NVGPU_MC_INTR_NONSTALLING,
+};
+
 void gp10b_init_mc(struct gpu_ops *gops);
 void mc_gp10b_intr_enable(struct gk20a *g);
+void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
+                bool is_stalling, u32 mask);
 irqreturn_t mc_gp10b_isr_stall(struct gk20a *g);
 irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g);
 irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g);