gpu: nvgpu: Split non-stall interrupt handling

Split handling of stalling interrupt to Linux specific chip
agnostic and OS independent chip specific parts.

Linux specific chip independent part contains handler for ISR
and passing the control to a bottom half worker. It uses the new MC
HALs intr_nonstall (query interrupt status), intr_nonstall_pause
(pause interrupts), intr_nonstall_resume (resume interrupts), and
is_intr1_pending (query per-engine interrupt bit).

MC HAL isr_nonstall is removed, because its work is now handled in
chip independent code.

JIRA NVGPU-26

Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497048
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
index 31867a88..ceba0b39 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
@@ -25,6 +25,4 @@ void mc_gp10b_intr_enable(struct gk20a *g);
 void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
                 bool is_stalling, u32 mask);
 void mc_gp10b_isr_stall(struct gk20a *g);
-irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g);
-irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g);
 #endif