Revert "gpu: nvgpu: change stall intr handling order"

This reverts commit 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 as
it caused lp0 suspend/resume failure.

Bug 1886110

Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index dfcbe398..abbd2191 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP20B master
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -133,12 +133,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 
         gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
-        /* handle critical interrupts first */
-        if (mc_intr_0 & mc_intr_pbus_pending_f())
-                gk20a_pbus_isr(g);
-        if (mc_intr_0 & mc_intr_priv_ring_pending_f())
-                gk20a_priv_ring_isr(g);
-
         for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
                 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
 
@@ -163,8 +157,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
                 gk20a_fifo_isr(g);
         if (mc_intr_0 & mc_intr_pmu_pending_f())
                 gk20a_pmu_isr(g);
+        if (mc_intr_0 & mc_intr_priv_ring_pending_f())
+                gk20a_priv_ring_isr(g);
         if (mc_intr_0 & mc_intr_ltc_pending_f())
                 g->ops.ltc.isr(g);
+        if (mc_intr_0 & mc_intr_pbus_pending_f())
+                gk20a_pbus_isr(g);
 
         /* sync handled irq counter before re-enabling interrupts */
         atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);