gpu: nvgpu: Add bus HAL

Add bus HAL and move all bus related hardware sequencing to that file:
BAR1 binding, timer access, and interrupt handling.

Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323353
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index fc0e6553..547169ed 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -162,7 +162,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
         if (mc_intr_0 & mc_intr_ltc_pending_f())
                 g->ops.ltc.isr(g);
         if (mc_intr_0 & mc_intr_pbus_pending_f())
-                gk20a_pbus_isr(g);
+                g->ops.bus.isr(g);
 
         /* sync handled irq counter before re-enabling interrupts */
         atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);