gpu: nvgpu: gp10b: add ce interrupt support

ce interrupts use different register mapping
and format from gk20a and gm20b.

Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 1760b6ad..47c8fcc6 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -110,6 +110,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 
         if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
                 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
+        if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+                && g->ops.ce2.isr_stall)
+                g->ops.ce2.isr_stall(g);
         if (mc_intr_0 & mc_intr_pfifo_pending_f())
                 gk20a_fifo_isr(g);
         if (mc_intr_0 & mc_intr_pmu_pending_f())
@@ -141,6 +144,11 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
                 gk20a_fifo_nonstall_isr(g);
         if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
                 gk20a_gr_nonstall_isr(g);
+        if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+                && g->ops.ce2.isr_nonstall)
+                g->ops.ce2.isr_nonstall(g);
+
+
 
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);