gpu: nvgpu: mask intr before gpu power off

once gpu is powered off i.e. power_on set to false, nvgpu isr
does not handle stall/nonstall irq. Depending upon state
of gpu, this can result in either of following errors:

1) irq 458: nobody cared (try booting with the "irqpoll" option)
2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is
not in time.

Fix these by masking all interrupts just before gpu power off
as nvgpu won't be handling any irq anymore.

While masking interrupts, if there are any pending interrupts,
then report those with a log message.

Bug 1987855
Bug 200424832

Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770802
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 56db6750..063bda7c 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -32,6 +32,17 @@
 
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
 
+#define MAX_MC_INTR_REGS        2U
+
+void mc_gp10b_intr_mask(struct gk20a *g)
+{
+        nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffffU);
+
+        nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffffU);
+}
+
 void mc_gp10b_intr_enable(struct gk20a *g)
 {
         u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
@@ -195,3 +206,17 @@ bool mc_gp10b_is_intr1_pending(struct gk20a *g,
 
         return is_pending;
 }
+
+void mc_gp10b_log_pending_intrs(struct gk20a *g)
+{
+        u32 i, intr;
+
+        for (i = 0; i < MAX_MC_INTR_REGS; i++) {
+                intr = nvgpu_readl(g, mc_intr_r(i));
+                if (intr == 0U) {
+                        continue;
+                }
+                nvgpu_info(g, "Pending intr%d=0x%08x", i, intr);
+        }
+
+}