diff options
author | Adeel Raza <araza@nvidia.com> | 2015-06-18 19:31:50 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:10 -0500 |
commit | f17e0d822b47465cca23afa2054bfa1267b52b95 (patch) | |
tree | b0e2c8953d1e2296c9d1a3b7207ff8546e6d0249 /drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |
parent | 4c5bc9c93b86d9de022d6baff343217f1d047a62 (diff) |
gpu: nvgpu: gp10b: add ECC support
Add ECC exception handling support for SM, TEX, and LTC.
Bug 1635727
Bug 1637486
Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ltc_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 47992988..d0be86a4 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -136,6 +136,20 @@ static void gp10b_ltc_isr(struct gk20a *g) | |||
136 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + | 136 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + |
137 | proj_ltc_stride_v() * ltc + | 137 | proj_ltc_stride_v() * ltc + |
138 | proj_lts_stride_v() * slice); | 138 | proj_lts_stride_v() * slice); |
139 | |||
140 | /* Detect and handle ECC errors */ | ||
141 | if (ltc_intr & | ||
142 | ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) { | ||
143 | gk20a_err(dev_from_gk20a(g), | ||
144 | "Single bit error detected in GPU L2!"); | ||
145 | g->ops.mm.l2_flush(g, true); | ||
146 | } | ||
147 | if (ltc_intr & | ||
148 | ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) { | ||
149 | gk20a_err(dev_from_gk20a(g), | ||
150 | "Double bit error detected in GPU L2!"); | ||
151 | } | ||
152 | |||
139 | gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", | 153 | gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", |
140 | ltc, slice, ltc_intr); | 154 | ltc, slice, ltc_intr); |
141 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | 155 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + |
@@ -148,10 +162,19 @@ static void gp10b_ltc_isr(struct gk20a *g) | |||
148 | 162 | ||
149 | static void gp10b_ltc_init_fs_state(struct gk20a *g) | 163 | static void gp10b_ltc_init_fs_state(struct gk20a *g) |
150 | { | 164 | { |
165 | u32 ltc_intr; | ||
166 | |||
151 | gm20b_ltc_init_fs_state(g); | 167 | gm20b_ltc_init_fs_state(g); |
152 | 168 | ||
153 | gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), | 169 | gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), |
154 | ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); | 170 | ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); |
171 | |||
172 | /* Enable ECC interrupts */ | ||
173 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | ||
174 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | | ||
175 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); | ||
176 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), | ||
177 | ltc_intr); | ||
155 | } | 178 | } |
156 | 179 | ||
157 | void gp10b_init_ltc(struct gpu_ops *gops) | 180 | void gp10b_init_ltc(struct gpu_ops *gops) |