gpu: nvgpu: gp10b: add ECC stats sysfs nodes

Add sysfs nodes for querying ECC single/double bit error counts.

Bug 1699676

Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 30 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index d0be86a4..e68e762d 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -133,21 +133,48 @@ static void gp10b_ltc_isr(struct gk20a *g)
                 if ((mc_intr & 1 << ltc) == 0)
                         continue;
                 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
-                        ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() +
-                                           proj_ltc_stride_v() * ltc +
-                                           proj_lts_stride_v() * slice);
+                        u32 offset = proj_ltc_stride_v() * ltc +
+                                        proj_lts_stride_v() * slice;
+                        ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
 
                         /* Detect and handle ECC errors */
                         if (ltc_intr &
                                 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) {
+                                u32 ecc_stats_reg_val;
+
                                 gk20a_err(dev_from_gk20a(g),
                                         "Single bit error detected in GPU L2!");
+
+                                ecc_stats_reg_val =
+                                        gk20a_readl(g,
+                                                ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
+                                g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] +=
+                                        ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
+                                ecc_stats_reg_val &=
+                                        ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
+                                gk20a_writel(g,
+                                        ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
+                                        ecc_stats_reg_val);
+
                                 g->ops.mm.l2_flush(g, true);
                         }
                         if (ltc_intr &
                                 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) {
+                                u32 ecc_stats_reg_val;
+
                                 gk20a_err(dev_from_gk20a(g),
                                         "Double bit error detected in GPU L2!");
+
+                                ecc_stats_reg_val =
+                                        gk20a_readl(g,
+                                                ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
+                                g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] +=
+                                        ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
+                                ecc_stats_reg_val &=
+                                        ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
+                                gk20a_writel(g,
+                                        ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
+                                        ecc_stats_reg_val);
                         }
 
                         gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x",