diff options
author | Adeel Raza <araza@nvidia.com> | 2014-10-02 23:39:32 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:01 -0500 |
commit | badee8f41a6304817b66287e39d81b382c575163 (patch) | |
tree | d7f603b53876032bf6d8fd6f86d825d6777493ed /drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | |
parent | dfdd5ba3cbc52f7359188783159b103d1d2edcf2 (diff) |
gpu: nvgpu: headers for linsim CL 33688874
Bug 1561645
Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/553151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h index 76597f69..94da91b0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | |||
@@ -200,11 +200,11 @@ static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) | |||
200 | } | 200 | } |
201 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) | 201 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) |
202 | { | 202 | { |
203 | return 0x00134124 + i*512; | 203 | return 0x001e0124 + i*1024; |
204 | } | 204 | } |
205 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | 205 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) |
206 | { | 206 | { |
207 | return (v & 0x3fff) << 0; | 207 | return (v & 0xffff) << 0; |
208 | } | 208 | } |
209 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | 209 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) |
210 | { | 210 | { |
@@ -220,11 +220,11 @@ static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | |||
220 | } | 220 | } |
221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) | 221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) |
222 | { | 222 | { |
223 | return 0x00134128 + i*512; | 223 | return 0x001e0128 + i*1024; |
224 | } | 224 | } |
225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) | 225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) |
226 | { | 226 | { |
227 | return (r >> 0) & 0xfffff; | 227 | return (r >> 0) & 0xfffffff; |
228 | } | 228 | } |
229 | static inline u32 trim_sys_gpcpll_cfg2_r(void) | 229 | static inline u32 trim_sys_gpcpll_cfg2_r(void) |
230 | { | 230 | { |