diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-10-27 03:47:25 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:02 -0500 |
commit | 07b7a534fa8d5e93420521fcb5e745acad386f00 (patch) | |
tree | f844c36ed9eea3731c5317cda19a1b7135e3e5b3 /drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | |
parent | 1f3b9d851a0beb716596040f77b1431cc1fd8670 (diff) |
gpu: nvgpu: Synchronize gp10b headers with gm20b
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.
Bug 1567274
Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 289 |
1 files changed, 0 insertions, 289 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h deleted file mode 100644 index 94da91b0..00000000 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ /dev/null | |||
@@ -1,289 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_trim_gp10b_h_ | ||
51 | #define _hw_trim_gp10b_h_ | ||
52 | |||
53 | static inline u32 trim_sys_gpcpll_cfg_r(void) | ||
54 | { | ||
55 | return 0x00137000; | ||
56 | } | ||
57 | static inline u32 trim_sys_gpcpll_cfg_enable_m(void) | ||
58 | { | ||
59 | return 0x1 << 0; | ||
60 | } | ||
61 | static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) | ||
62 | { | ||
63 | return (r >> 0) & 0x1; | ||
64 | } | ||
65 | static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) | ||
70 | { | ||
71 | return 0x1; | ||
72 | } | ||
73 | static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) | ||
74 | { | ||
75 | return 0x1 << 1; | ||
76 | } | ||
77 | static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) | ||
78 | { | ||
79 | return (r >> 1) & 0x1; | ||
80 | } | ||
81 | static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) | ||
82 | { | ||
83 | return 0x00000000; | ||
84 | } | ||
85 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) | ||
86 | { | ||
87 | return 0x1 << 4; | ||
88 | } | ||
89 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) | ||
90 | { | ||
91 | return 0x0; | ||
92 | } | ||
93 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) | ||
94 | { | ||
95 | return 0x10; | ||
96 | } | ||
97 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) | ||
98 | { | ||
99 | return (r >> 17) & 0x1; | ||
100 | } | ||
101 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) | ||
102 | { | ||
103 | return 0x20000; | ||
104 | } | ||
105 | static inline u32 trim_sys_gpcpll_coeff_r(void) | ||
106 | { | ||
107 | return 0x00137004; | ||
108 | } | ||
109 | static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) | ||
110 | { | ||
111 | return (v & 0xff) << 0; | ||
112 | } | ||
113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) | ||
114 | { | ||
115 | return (r >> 0) & 0xff; | ||
116 | } | ||
117 | static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) | ||
118 | { | ||
119 | return (v & 0xff) << 8; | ||
120 | } | ||
121 | static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) | ||
122 | { | ||
123 | return 0xff << 8; | ||
124 | } | ||
125 | static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) | ||
126 | { | ||
127 | return (r >> 8) & 0xff; | ||
128 | } | ||
129 | static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x3f) << 16; | ||
132 | } | ||
133 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) | ||
134 | { | ||
135 | return (r >> 16) & 0x3f; | ||
136 | } | ||
137 | static inline u32 trim_sys_sel_vco_r(void) | ||
138 | { | ||
139 | return 0x00137100; | ||
140 | } | ||
141 | static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) | ||
142 | { | ||
143 | return 0x1 << 0; | ||
144 | } | ||
145 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) | ||
146 | { | ||
147 | return 0x00000000; | ||
148 | } | ||
149 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) | ||
150 | { | ||
151 | return 0x0; | ||
152 | } | ||
153 | static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) | ||
158 | { | ||
159 | return 0x1; | ||
160 | } | ||
161 | static inline u32 trim_sys_gpc2clk_out_r(void) | ||
162 | { | ||
163 | return 0x00137250; | ||
164 | } | ||
165 | static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) | ||
166 | { | ||
167 | return 6; | ||
168 | } | ||
169 | static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x3f) << 0; | ||
172 | } | ||
173 | static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) | ||
174 | { | ||
175 | return 0x3f << 0; | ||
176 | } | ||
177 | static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) | ||
178 | { | ||
179 | return (r >> 0) & 0x3f; | ||
180 | } | ||
181 | static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) | ||
182 | { | ||
183 | return 0x3c; | ||
184 | } | ||
185 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) | ||
186 | { | ||
187 | return 0x3f << 8; | ||
188 | } | ||
189 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) | ||
190 | { | ||
191 | return 0x0; | ||
192 | } | ||
193 | static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) | ||
194 | { | ||
195 | return 0x1 << 31; | ||
196 | } | ||
197 | static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) | ||
198 | { | ||
199 | return 0x80000000; | ||
200 | } | ||
201 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) | ||
202 | { | ||
203 | return 0x001e0124 + i*1024; | ||
204 | } | ||
205 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | ||
206 | { | ||
207 | return (v & 0xffff) << 0; | ||
208 | } | ||
209 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | ||
210 | { | ||
211 | return 0x10000; | ||
212 | } | ||
213 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) | ||
214 | { | ||
215 | return 0x100000; | ||
216 | } | ||
217 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | ||
218 | { | ||
219 | return 0x1000000; | ||
220 | } | ||
221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) | ||
222 | { | ||
223 | return 0x001e0128 + i*1024; | ||
224 | } | ||
225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0xfffffff; | ||
228 | } | ||
229 | static inline u32 trim_sys_gpcpll_cfg2_r(void) | ||
230 | { | ||
231 | return 0x0013700c; | ||
232 | } | ||
233 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) | ||
234 | { | ||
235 | return (v & 0xff) << 24; | ||
236 | } | ||
237 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) | ||
238 | { | ||
239 | return 0xff << 24; | ||
240 | } | ||
241 | static inline u32 trim_sys_gpcpll_cfg3_r(void) | ||
242 | { | ||
243 | return 0x00137018; | ||
244 | } | ||
245 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) | ||
246 | { | ||
247 | return (v & 0xff) << 16; | ||
248 | } | ||
249 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) | ||
250 | { | ||
251 | return 0xff << 16; | ||
252 | } | ||
253 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) | ||
254 | { | ||
255 | return 0x0013701c; | ||
256 | } | ||
257 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) | ||
258 | { | ||
259 | return 0x1 << 22; | ||
260 | } | ||
261 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) | ||
262 | { | ||
263 | return 0x400000; | ||
264 | } | ||
265 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) | ||
266 | { | ||
267 | return 0x0; | ||
268 | } | ||
269 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) | ||
270 | { | ||
271 | return 0x1 << 31; | ||
272 | } | ||
273 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) | ||
274 | { | ||
275 | return 0x80000000; | ||
276 | } | ||
277 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) | ||
278 | { | ||
279 | return 0x0; | ||
280 | } | ||
281 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) | ||
282 | { | ||
283 | return 0x001328a0; | ||
284 | } | ||
285 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) | ||
286 | { | ||
287 | return (r >> 24) & 0x1; | ||
288 | } | ||
289 | #endif | ||