gpu: nvgpu: Synchronize gp10b headers with gm20b

Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.

Bug 1567274

Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit

1 files changed, 39 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
index 83e06e8e..ba0af497 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
@@ -50,38 +50,62 @@
 #ifndef _hw_mc_gp10b_h_
 #define _hw_mc_gp10b_h_
 
-static inline u32 mc_intr_0_r(u32 i)
+static inline u32 mc_boot_0_r(void)
 {
-        return 0x00000100 + i*4;
+        return 0x00000000;
 }
-static inline u32 mc_intr_0_pfifo_pending_f(void)
+static inline u32 mc_boot_0_architecture_v(u32 r)
 {
-        return 0x100;
+        return (r >> 24) & 0x1f;
 }
-static inline u32 mc_intr_0_pgraph_pending_f(void)
+static inline u32 mc_boot_0_implementation_v(u32 r)
 {
-        return 0x1000;
+        return (r >> 20) & 0xf;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4) & 0xf;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100 + i*4;
 }
-static inline u32 mc_intr_0_pmu_pending_f(void)
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
 {
         return 0x1000000;
 }
-static inline u32 mc_intr_0_ltc_pending_f(void)
+static inline u32 mc_intr_ltc_pending_f(void)
 {
         return 0x2000000;
 }
-static inline u32 mc_intr_0_priv_ring_pending_f(void)
+static inline u32 mc_intr_priv_ring_pending_f(void)
 {
         return 0x40000000;
 }
-static inline u32 mc_intr_0_pbus_pending_f(void)
+static inline u32 mc_intr_pbus_pending_f(void)
 {
         return 0x10000000;
 }
-static inline u32 mc_intr_en_0_r(u32 i)
+static inline u32 mc_intr_en_r(u32 i)
 {
         return 0x00000140 + i*4;
 }
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+        return 0x00000160 + i*4;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+        return 0x00000180 + i*4;
+}
 static inline u32 mc_enable_r(void)
 {
         return 0x00000200;
@@ -162,6 +186,10 @@ static inline u32 mc_enable_hub_enabled_f(void)
 {
         return 0x20000000;
 }
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x000001c0;
+}
 static inline u32 mc_enable_pb_r(void)
 {
         return 0x00000204;