diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-10-27 03:47:25 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:02 -0500 |
commit | 07b7a534fa8d5e93420521fcb5e745acad386f00 (patch) | |
tree | f844c36ed9eea3731c5317cda19a1b7135e3e5b3 /drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |
parent | 1f3b9d851a0beb716596040f77b1431cc1fd8670 (diff) |
gpu: nvgpu: Synchronize gp10b headers with gm20b
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.
Bug 1567274
Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 228 |
1 files changed, 136 insertions, 92 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 03164957..f8607618 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void) | |||
78 | { | 78 | { |
79 | return 0x10; | 79 | return 0x10; |
80 | } | 80 | } |
81 | static inline u32 gr_intr_illegal_notify_pending_f(void) | ||
82 | { | ||
83 | return 0x40; | ||
84 | } | ||
85 | static inline u32 gr_intr_illegal_notify_reset_f(void) | ||
86 | { | ||
87 | return 0x40; | ||
88 | } | ||
89 | static inline u32 gr_intr_firmware_method_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 8; | ||
92 | } | ||
93 | static inline u32 gr_intr_firmware_method_pending_f(void) | ||
94 | { | ||
95 | return 0x100; | ||
96 | } | ||
97 | static inline u32 gr_intr_firmware_method_reset_f(void) | ||
98 | { | ||
99 | return 0x100; | ||
100 | } | ||
81 | static inline u32 gr_intr_illegal_class_pending_f(void) | 101 | static inline u32 gr_intr_illegal_class_pending_f(void) |
82 | { | 102 | { |
83 | return 0x20; | 103 | return 0x20; |
@@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void) | |||
86 | { | 106 | { |
87 | return 0x20; | 107 | return 0x20; |
88 | } | 108 | } |
109 | static inline u32 gr_intr_fecs_error_pending_f(void) | ||
110 | { | ||
111 | return 0x80000; | ||
112 | } | ||
113 | static inline u32 gr_intr_fecs_error_reset_f(void) | ||
114 | { | ||
115 | return 0x80000; | ||
116 | } | ||
89 | static inline u32 gr_intr_class_error_pending_f(void) | 117 | static inline u32 gr_intr_class_error_pending_f(void) |
90 | { | 118 | { |
91 | return 0x100000; | 119 | return 0x100000; |
@@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void) | |||
102 | { | 130 | { |
103 | return 0x200000; | 131 | return 0x200000; |
104 | } | 132 | } |
133 | static inline u32 gr_fecs_intr_r(void) | ||
134 | { | ||
135 | return 0x00400144; | ||
136 | } | ||
137 | static inline u32 gr_class_error_r(void) | ||
138 | { | ||
139 | return 0x00400110; | ||
140 | } | ||
141 | static inline u32 gr_class_error_code_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0xffff; | ||
144 | } | ||
145 | static inline u32 gr_intr_nonstall_r(void) | ||
146 | { | ||
147 | return 0x00400120; | ||
148 | } | ||
149 | static inline u32 gr_intr_nonstall_trap_pending_f(void) | ||
150 | { | ||
151 | return 0x2; | ||
152 | } | ||
105 | static inline u32 gr_intr_en_r(void) | 153 | static inline u32 gr_intr_en_r(void) |
106 | { | 154 | { |
107 | return 0x0040013c; | 155 | return 0x0040013c; |
@@ -198,6 +246,10 @@ static inline u32 gr_status_r(void) | |||
198 | { | 246 | { |
199 | return 0x00400700; | 247 | return 0x00400700; |
200 | } | 248 | } |
249 | static inline u32 gr_status_fe_method_upper_v(u32 r) | ||
250 | { | ||
251 | return (r >> 1) & 0x1; | ||
252 | } | ||
201 | static inline u32 gr_status_fe_method_lower_v(u32 r) | 253 | static inline u32 gr_status_fe_method_lower_v(u32 r) |
202 | { | 254 | { |
203 | return (r >> 2) & 0x1; | 255 | return (r >> 2) & 0x1; |
@@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void) | |||
206 | { | 258 | { |
207 | return 0x00000000; | 259 | return 0x00000000; |
208 | } | 260 | } |
261 | static inline u32 gr_status_fe_gi_v(u32 r) | ||
262 | { | ||
263 | return (r >> 21) & 0x1; | ||
264 | } | ||
209 | static inline u32 gr_status_mask_r(void) | 265 | static inline u32 gr_status_mask_r(void) |
210 | { | 266 | { |
211 | return 0x00400610; | 267 | return 0x00400610; |
@@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
662 | { | 718 | { |
663 | return 0x21; | 719 | return 0x21; |
664 | } | 720 | } |
721 | static inline u32 gr_fecs_host_int_status_r(void) | ||
722 | { | ||
723 | return 0x00409c18; | ||
724 | } | ||
725 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
726 | { | ||
727 | return (v & 0x1) << 17; | ||
728 | } | ||
729 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
730 | { | ||
731 | return (v & 0x1) << 18; | ||
732 | } | ||
733 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
734 | { | ||
735 | return 0x00409c20; | ||
736 | } | ||
665 | static inline u32 gr_fecs_host_int_enable_r(void) | 737 | static inline u32 gr_fecs_host_int_enable_r(void) |
666 | { | 738 | { |
667 | return 0x00409c24; | 739 | return 0x00409c24; |
@@ -1292,15 +1364,19 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | |||
1292 | } | 1364 | } |
1293 | static inline u32 gr_ds_tga_constraintlogic_r(void) | 1365 | static inline u32 gr_ds_tga_constraintlogic_r(void) |
1294 | { | 1366 | { |
1295 | return 0xffffffff; | 1367 | return 0x00405830; |
1296 | } | 1368 | } |
1297 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | 1369 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) |
1298 | { | 1370 | { |
1299 | return (v & 0x1) << -1; | 1371 | return (v & 0x3fffff) << 0; |
1372 | } | ||
1373 | static inline u32 gr_ds_tga_constraintlogic_r(void) | ||
1374 | { | ||
1375 | return 0x0040585c; | ||
1300 | } | 1376 | } |
1301 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) | 1377 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) |
1302 | { | 1378 | { |
1303 | return (v & 0x1) << -1; | 1379 | return (v & 0xffff) << 0; |
1304 | } | 1380 | } |
1305 | static inline u32 gr_ds_hww_esr_r(void) | 1381 | static inline u32 gr_ds_hww_esr_r(void) |
1306 | { | 1382 | { |
@@ -1674,6 +1750,34 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) | |||
1674 | { | 1750 | { |
1675 | return (r >> 0) & 0x3f; | 1751 | return (r >> 0) & 0x3f; |
1676 | } | 1752 | } |
1753 | static inline u32 gr_gpccs_rc_lane_size_r(void) | ||
1754 | { | ||
1755 | return 0x00502910; | ||
1756 | } | ||
1757 | static inline u32 gr_gpccs_rc_lane_size_v_s(void) | ||
1758 | { | ||
1759 | return 24; | ||
1760 | } | ||
1761 | static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) | ||
1762 | { | ||
1763 | return (v & 0xffffff) << 0; | ||
1764 | } | ||
1765 | static inline u32 gr_gpccs_rc_lane_size_v_m(void) | ||
1766 | { | ||
1767 | return 0xffffff << 0; | ||
1768 | } | ||
1769 | static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) | ||
1770 | { | ||
1771 | return (r >> 0) & 0xffffff; | ||
1772 | } | ||
1773 | static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) | ||
1774 | { | ||
1775 | return 0x00000000; | ||
1776 | } | ||
1777 | static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) | ||
1778 | { | ||
1779 | return 0x0; | ||
1780 | } | ||
1677 | static inline u32 gr_gpc0_zcull_fs_r(void) | 1781 | static inline u32 gr_gpc0_zcull_fs_r(void) |
1678 | { | 1782 | { |
1679 | return 0x00500910; | 1783 | return 0x00500910; |
@@ -2068,19 +2172,11 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) | |||
2068 | } | 2172 | } |
2069 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) | 2173 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) |
2070 | { | 2174 | { |
2071 | return (v & 0xffffffff) << -1; | 2175 | return (v & 0x3fffff) << 0; |
2072 | } | 2176 | } |
2073 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | 2177 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) |
2074 | { | 2178 | { |
2075 | return 0xffffffff << -1; | 2179 | return 0x3fffff << 0; |
2076 | } | ||
2077 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) | ||
2078 | { | ||
2079 | return (v & 0xffffffff) << -1; | ||
2080 | } | ||
2081 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) | ||
2082 | { | ||
2083 | return 0xffffffff << -1; | ||
2084 | } | 2180 | } |
2085 | static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) | 2181 | static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) |
2086 | { | 2182 | { |
@@ -2526,26 +2622,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
2526 | { | 2622 | { |
2527 | return 0x10000000; | 2623 | return 0x10000000; |
2528 | } | 2624 | } |
2529 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) | ||
2530 | { | ||
2531 | return 0x00419e00; | ||
2532 | } | ||
2533 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) | ||
2534 | { | ||
2535 | return 0x1 << 7; | ||
2536 | } | ||
2537 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) | ||
2538 | { | ||
2539 | return 0x80; | ||
2540 | } | ||
2541 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) | ||
2542 | { | ||
2543 | return 0x1 << 15; | ||
2544 | } | ||
2545 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) | ||
2546 | { | ||
2547 | return 0x8000; | ||
2548 | } | ||
2549 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | 2625 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) |
2550 | { | 2626 | { |
2551 | return 0x00419e44; | 2627 | return 0x00419e44; |
@@ -2670,51 +2746,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
2670 | { | 2746 | { |
2671 | return 0x40; | 2747 | return 0x40; |
2672 | } | 2748 | } |
2673 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | 2749 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
2674 | { | 2750 | { |
2675 | return 0x0050450c; | 2751 | return 0x00419d0c; |
2676 | } | 2752 | } |
2677 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | 2753 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) |
2678 | { | 2754 | { |
2679 | return 0x2; | 2755 | return 0x2; |
2680 | } | 2756 | } |
2681 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) | 2757 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) |
2682 | { | 2758 | { |
2683 | return 0x0; | 2759 | return 0x0050450c; |
2684 | } | 2760 | } |
2685 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) | 2761 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) |
2686 | { | 2762 | { |
2687 | return 0x00502c94; | 2763 | return 0x2; |
2688 | } | 2764 | } |
2689 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) | 2765 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) |
2690 | { | 2766 | { |
2691 | return 0x10000; | 2767 | return 0x0041ac94; |
2692 | } | 2768 | } |
2693 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) | 2769 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) |
2694 | { | 2770 | { |
2695 | return 0x0; | 2771 | return (v & 0xff) << 16; |
2696 | } | 2772 | } |
2697 | static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) | 2773 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) |
2698 | { | 2774 | { |
2699 | return 0x0041ac90; | 2775 | return 0x00502c90; |
2700 | } | 2776 | } |
2701 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) | 2777 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) |
2702 | { | 2778 | { |
2703 | return (r >> 16) & 0xff; | 2779 | return (r >> 16) & 0xff; |
2704 | } | 2780 | } |
2705 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) | 2781 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) |
2706 | { | 2782 | { |
2707 | return 0x00000001; | 2783 | return 0x00000001; |
2708 | } | 2784 | } |
2709 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) | 2785 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) |
2710 | { | 2786 | { |
2711 | return 0x00419d08; | 2787 | return 0x00504508; |
2712 | } | 2788 | } |
2713 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) | 2789 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) |
2714 | { | 2790 | { |
2715 | return (r >> 1) & 0x1; | 2791 | return (r >> 1) & 0x1; |
2716 | } | 2792 | } |
2717 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) | 2793 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) |
2718 | { | 2794 | { |
2719 | return 0x00000001; | 2795 | return 0x00000001; |
2720 | } | 2796 | } |
@@ -2810,10 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | |||
2810 | { | 2886 | { |
2811 | return (v & 0x1) << 0; | 2887 | return (v & 0x1) << 0; |
2812 | } | 2888 | } |
2813 | static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) | ||
2814 | { | ||
2815 | return 0x00419ed8; | ||
2816 | } | ||
2817 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | 2889 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) |
2818 | { | 2890 | { |
2819 | return 0x0041be08; | 2891 | return 0x0041be08; |
@@ -3078,42 +3150,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void) | |||
3078 | { | 3150 | { |
3079 | return 0x00000000; | 3151 | return 0x00000000; |
3080 | } | 3152 | } |
3081 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) | ||
3082 | { | ||
3083 | return 0x00419f88; | ||
3084 | } | ||
3085 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) | ||
3086 | { | ||
3087 | return (v & 0x1) << 31; | ||
3088 | } | ||
3089 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) | ||
3090 | { | ||
3091 | return 0x1 << 31; | ||
3092 | } | ||
3093 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) | ||
3094 | { | ||
3095 | return 0x00419f80; | ||
3096 | } | ||
3097 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) | ||
3098 | { | ||
3099 | return (v & 0x1) << 31; | ||
3100 | } | ||
3101 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) | ||
3102 | { | ||
3103 | return 0x1 << 31; | ||
3104 | } | ||
3105 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) | ||
3106 | { | ||
3107 | return 0x00419ccc; | ||
3108 | } | ||
3109 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) | ||
3110 | { | ||
3111 | return (v & 0x1) << 31; | ||
3112 | } | ||
3113 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) | ||
3114 | { | ||
3115 | return 0x1 << 31; | ||
3116 | } | ||
3117 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | 3153 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) |
3118 | { | 3154 | { |
3119 | return 0x00418880; | 3155 | return 0x00418880; |
@@ -3166,6 +3202,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | |||
3166 | { | 3202 | { |
3167 | return 0x004188b0; | 3203 | return 0x004188b0; |
3168 | } | 3204 | } |
3205 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) | ||
3206 | { | ||
3207 | return (r >> 16) & 0x1; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) | ||
3210 | { | ||
3211 | return 0x00000001; | ||
3212 | } | ||
3169 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | 3213 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) |
3170 | { | 3214 | { |
3171 | return 0x004188b4; | 3215 | return 0x004188b4; |