gpu: nvgpu: gp10b: Fix PDE/PTE address handling

We were dropping the part of address that span word bounary. The register
generator does not know how to real with multi-word fields, to edit things
in manually.

Bug 1646531

Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/747468

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
index fc65f57d..844cb142 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
@@ -72,7 +72,7 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
 }
 static inline u32 gmmu_new_pde_address_sys_f(u32 v)
 {
-        return (v & 0xffffff) << 8;
+        return (v & 0xfffffff) << 8;
 }
 static inline u32 gmmu_new_pde_address_sys_w(void)
 {
@@ -164,7 +164,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
 {
-        return (v & 0xffffff) << 8;
+        return (v & 0xfffffff) << 8;
 }
 static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
 {
@@ -200,7 +200,7 @@ static inline u32 gmmu_new_pte_valid_false_f(void)
 }
 static inline u32 gmmu_new_pte_address_sys_f(u32 v)
 {
-        return (v & 0xffffff) << 8;
+        return (v & 0xfffffff) << 8;
 }
 static inline u32 gmmu_new_pte_address_sys_w(void)
 {