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authorSunny He <suhe@nvidia.com>2017-06-28 17:16:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-26 05:44:23 -0400
commitde3ad1a94974b08268a485136f04b8e436ef2579 (patch)
tree15910cd769e91f6600fef0546b501faf65e1fa50 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c
parent92f6eb016cc759b24e249ed6c17cff537cc35db7 (diff)
gpu: nvgpu: Remove securegpccs flag from gpu_ops
Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 177a7c9f..818949f0 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -369,36 +369,36 @@ int gp10b_init_hal(struct gk20a *g)
369#ifdef CONFIG_TEGRA_ACR 369#ifdef CONFIG_TEGRA_ACR
370 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 370 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
371 gops->privsecurity = 0; 371 gops->privsecurity = 0;
372 gops->securegpccs = 0; 372 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
373 } else if (g->is_virtual) { 373 } else if (g->is_virtual) {
374 gops->privsecurity = 1; 374 gops->privsecurity = 1;
375 gops->securegpccs = 1; 375 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
376 } else { 376 } else {
377 val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); 377 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
378 if (val) { 378 if (val) {
379 gops->privsecurity = 1; 379 gops->privsecurity = 1;
380 gops->securegpccs =1; 380 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
381 } else { 381 } else {
382 gk20a_dbg_info("priv security is disabled in HW"); 382 gk20a_dbg_info("priv security is disabled in HW");
383 gops->privsecurity = 0; 383 gops->privsecurity = 0;
384 gops->securegpccs = 0; 384 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
385 } 385 }
386 } 386 }
387#else 387#else
388 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 388 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
389 gk20a_dbg_info("running simulator with PRIV security disabled"); 389 gk20a_dbg_info("running simulator with PRIV security disabled");
390 gops->privsecurity = 0; 390 gops->privsecurity = 0;
391 gops->securegpccs = 0; 391 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
392 } else { 392 } else {
393 val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); 393 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
394 if (val) { 394 if (val) {
395 gk20a_dbg_info("priv security is not supported but enabled"); 395 gk20a_dbg_info("priv security is not supported but enabled");
396 gops->privsecurity = 1; 396 gops->privsecurity = 1;
397 gops->securegpccs =1; 397 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
398 return -EPERM; 398 return -EPERM;
399 } else { 399 } else {
400 gops->privsecurity = 0; 400 gops->privsecurity = 0;
401 gops->securegpccs = 0; 401 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
402 } 402 }
403 } 403 }
404#endif 404#endif