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authorSunny He <suhe@nvidia.com>2017-07-24 15:18:38 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-26 05:45:14 -0400
commitd59271c7b79080388371877fc2d10574ca42206a (patch)
tree921f6d1ddce07235d7fbd1f27e6510b8cfe56ae7 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c
parentde3ad1a94974b08268a485136f04b8e436ef2579 (diff)
gpu: nvgpu: Remove privsecurity flag from gpu_ops
Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 818949f0..6b4fbf40 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -368,49 +368,49 @@ int gp10b_init_hal(struct gk20a *g)
368 368
369#ifdef CONFIG_TEGRA_ACR 369#ifdef CONFIG_TEGRA_ACR
370 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 370 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
371 gops->privsecurity = 0; 371 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
372 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 372 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
373 } else if (g->is_virtual) { 373 } else if (g->is_virtual) {
374 gops->privsecurity = 1; 374 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
375 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); 375 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
376 } else { 376 } else {
377 val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); 377 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
378 if (val) { 378 if (val) {
379 gops->privsecurity = 1; 379 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
380 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); 380 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
381 } else { 381 } else {
382 gk20a_dbg_info("priv security is disabled in HW"); 382 gk20a_dbg_info("priv security is disabled in HW");
383 gops->privsecurity = 0; 383 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
384 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 384 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
385 } 385 }
386 } 386 }
387#else 387#else
388 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 388 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
389 gk20a_dbg_info("running simulator with PRIV security disabled"); 389 gk20a_dbg_info("running simulator with PRIV security disabled");
390 gops->privsecurity = 0; 390 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
391 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 391 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
392 } else { 392 } else {
393 val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); 393 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
394 if (val) { 394 if (val) {
395 gk20a_dbg_info("priv security is not supported but enabled"); 395 gk20a_dbg_info("priv security is not supported but enabled");
396 gops->privsecurity = 1; 396 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
397 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); 397 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
398 return -EPERM; 398 return -EPERM;
399 } else { 399 } else {
400 gops->privsecurity = 0; 400 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
401 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 401 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
402 } 402 }
403 } 403 }
404#endif 404#endif
405 405
406 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; 406 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
407 gp10b_init_gr(gops); 407 gp10b_init_gr(g);
408 gp10b_init_fecs_trace_ops(gops); 408 gp10b_init_fecs_trace_ops(gops);
409 gp10b_init_fb(gops); 409 gp10b_init_fb(gops);
410 gp10b_init_ce(gops); 410 gp10b_init_ce(gops);
411 gp10b_init_gr_ctx(gops); 411 gp10b_init_gr_ctx(gops);
412 gp10b_init_mm(gops); 412 gp10b_init_mm(gops);
413 gp10b_init_pmu_ops(gops); 413 gp10b_init_pmu_ops(g);
414 gp10b_init_regops(gops); 414 gp10b_init_regops(gops);
415 gp10b_init_therm_ops(gops); 415 gp10b_init_therm_ops(gops);
416 gk20a_init_pramin_ops(gops); 416 gk20a_init_pramin_ops(gops);