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authorMahantesh Kumbar <mkumbar@nvidia.com>2015-08-28 19:42:29 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:07 -0500
commit71afbe484f0bda343f73c3afcfd5ca4205be4e09 (patch)
tree31c83d76c5f2ec278eb5c5ef24af068a5d41f2a8 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c
parente7ab0321d3502515a7ede0bd395e80e5783664fc (diff)
gpu: nvgpu: fuse read to boot in SECURE mode
-Read fuse to boot in secure/production mode else non sercure mode. Bug N/A Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/791323 Reviewed-on: http://git-master/r/806191 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c39
1 files changed, 38 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 983b985d..a6131cea 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -37,6 +37,10 @@
37#include "gm20b/fifo_gm20b.h" 37#include "gm20b/fifo_gm20b.h"
38#include "gm20b/pmu_gm20b.h" 38#include "gm20b/pmu_gm20b.h"
39#include "gm20b/clk_gm20b.h" 39#include "gm20b/clk_gm20b.h"
40#include <linux/tegra-fuse.h>
41
42#define FUSE_OPT_PRIV_SEC_EN_0 0x264
43#define PRIV_SECURITY_ENABLED 0x01
40 44
41static struct gpu_ops gp10b_ops = { 45static struct gpu_ops gp10b_ops = {
42 .clock_gating = { 46 .clock_gating = {
@@ -91,7 +95,40 @@ int gp10b_init_hal(struct gk20a *g)
91 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; 95 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
92 96
93 *gops = gp10b_ops; 97 *gops = gp10b_ops;
94 gops->privsecurity = 0; 98
99#ifdef CONFIG_TEGRA_ACR
100 if (tegra_platform_is_linsim()) {
101 gops->privsecurity = 1;
102 gops->securegpccs = 1;
103 } else {
104 if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
105 PRIV_SECURITY_ENABLED) {
106 gops->privsecurity = 1;
107 gops->securegpccs =1;
108 } else {
109 gk20a_dbg_info("priv security is disabled in HW");
110 gops->privsecurity = 0;
111 gops->securegpccs = 0;
112 }
113 }
114#else
115 if (tegra_platform_is_linsim()) {
116 gk20a_dbg_info("running ASIM with PRIV security disabled");
117 gops->privsecurity = 0;
118 gops->securegpccs = 0;
119 } else {
120 if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
121 PRIV_SECURITY_ENABLED) {
122 gk20a_dbg_info("priv security is not supported but enabled");
123 gops->privsecurity = 1;
124 gops->securegpccs =1;
125 return -EPERM;
126 } else {
127 gops->privsecurity = 0;
128 gops->securegpccs = 0;
129 }
130 }
131#endif
95 132
96 gp10b_init_mc(gops); 133 gp10b_init_mc(gops);
97 gp10b_init_gr(gops); 134 gp10b_init_gr(gops);