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authorSunny He <suhe@nvidia.com>2017-06-30 18:53:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-24 02:35:06 -0400
commit66ec347db401affd8bcd425dc123e7162b9ae3bb (patch)
treecbeb24e465208c6ab3b9527a86ba35003837f176 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c
parent2b582c5141752ff272c5d059b56433155bc3985a (diff)
gpu: nvgpu: Reorg fifo HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c68
1 files changed, 66 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 4479be42..d603703b 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -14,6 +14,7 @@
14 */ 14 */
15 15
16#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
17#include "gk20a/fifo_gk20a.h"
17#include "gk20a/dbg_gpu_gk20a.h" 18#include "gk20a/dbg_gpu_gk20a.h"
18#include "gk20a/css_gr_gk20a.h" 19#include "gk20a/css_gr_gk20a.h"
19#include "gk20a/bus_gk20a.h" 20#include "gk20a/bus_gk20a.h"
@@ -43,6 +44,7 @@
43#include "gm20b/fifo_gm20b.h" 44#include "gm20b/fifo_gm20b.h"
44#include "gm20b/pmu_gm20b.h" 45#include "gm20b/pmu_gm20b.h"
45#include "gm20b/clk_gm20b.h" 46#include "gm20b/clk_gm20b.h"
47#include "gm20b/fifo_gm20b.h"
46 48
47#include "gp10b.h" 49#include "gp10b.h"
48#include "hal_gp10b.h" 50#include "hal_gp10b.h"
@@ -54,6 +56,9 @@
54 56
55#include <nvgpu/hw/gp10b/hw_proj_gp10b.h> 57#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
56#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> 58#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
59#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
60#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
61#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
57 62
58static int gp10b_get_litter_value(struct gk20a *g, int value) 63static int gp10b_get_litter_value(struct gk20a *g, int value)
59{ 64{
@@ -210,6 +215,66 @@ static const struct gpu_ops gp10b_ops = {
210 .pg_gr_load_gating_prod = 215 .pg_gr_load_gating_prod =
211 gr_gp10b_pg_gr_load_gating_prod, 216 gr_gp10b_pg_gr_load_gating_prod,
212 }, 217 },
218 .fifo = {
219 .init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
220 .bind_channel = channel_gm20b_bind,
221 .unbind_channel = gk20a_fifo_channel_unbind,
222 .disable_channel = gk20a_fifo_disable_channel,
223 .enable_channel = gk20a_fifo_enable_channel,
224 .alloc_inst = gk20a_fifo_alloc_inst,
225 .free_inst = gk20a_fifo_free_inst,
226 .setup_ramfc = channel_gp10b_setup_ramfc,
227 .channel_set_priority = gk20a_fifo_set_priority,
228 .channel_set_timeslice = gk20a_fifo_set_timeslice,
229 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
230 .setup_userd = gk20a_fifo_setup_userd,
231 .userd_gp_get = gk20a_fifo_userd_gp_get,
232 .userd_gp_put = gk20a_fifo_userd_gp_put,
233 .userd_pb_get = gk20a_fifo_userd_pb_get,
234 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
235 .preempt_channel = gk20a_fifo_preempt_channel,
236 .preempt_tsg = gk20a_fifo_preempt_tsg,
237 .update_runlist = gk20a_fifo_update_runlist,
238 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
239 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
240 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
241 .get_num_fifos = gm20b_fifo_get_num_fifos,
242 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
243 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
244 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
245 .force_reset_ch = gk20a_fifo_force_reset_ch,
246 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
247 .device_info_data_parse = gp10b_device_info_data_parse,
248 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
249 .init_engine_info = gk20a_fifo_init_engine_info,
250 .runlist_entry_size = ram_rl_entry_size_v,
251 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
252 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
253 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
254 .dump_pbdma_status = gk20a_dump_pbdma_status,
255 .dump_eng_status = gk20a_dump_eng_status,
256 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
257 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
258 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
259 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
260 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
261 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
262 .handle_sched_error = gk20a_fifo_handle_sched_error,
263 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
264 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
265 .tsg_bind_channel = gk20a_tsg_bind_channel,
266 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
267#ifdef CONFIG_TEGRA_GK20A_NVHOST
268 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
269 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
270 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
271 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
272 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
273 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
274#endif
275 .resetup_ramfc = gp10b_fifo_resetup_ramfc,
276 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
277 },
213 .mc = { 278 .mc = {
214 .intr_enable = mc_gp10b_intr_enable, 279 .intr_enable = mc_gp10b_intr_enable,
215 .intr_unit_config = mc_gp10b_intr_unit_config, 280 .intr_unit_config = mc_gp10b_intr_unit_config,
@@ -281,6 +346,7 @@ int gp10b_init_hal(struct gk20a *g)
281 346
282 gops->ltc = gp10b_ops.ltc; 347 gops->ltc = gp10b_ops.ltc;
283 gops->clock_gating = gp10b_ops.clock_gating; 348 gops->clock_gating = gp10b_ops.clock_gating;
349 gops->fifo = gp10b_ops.fifo;
284 gops->mc = gp10b_ops.mc; 350 gops->mc = gp10b_ops.mc;
285 gops->debug = gp10b_ops.debug; 351 gops->debug = gp10b_ops.debug;
286 gops->dbg_session_ops = gp10b_ops.dbg_session_ops; 352 gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
@@ -340,14 +406,12 @@ int gp10b_init_hal(struct gk20a *g)
340 gp10b_init_gr(gops); 406 gp10b_init_gr(gops);
341 gp10b_init_fecs_trace_ops(gops); 407 gp10b_init_fecs_trace_ops(gops);
342 gp10b_init_fb(gops); 408 gp10b_init_fb(gops);
343 gp10b_init_fifo(gops);
344 gp10b_init_ce(gops); 409 gp10b_init_ce(gops);
345 gp10b_init_gr_ctx(gops); 410 gp10b_init_gr_ctx(gops);
346 gp10b_init_mm(gops); 411 gp10b_init_mm(gops);
347 gp10b_init_pmu_ops(gops); 412 gp10b_init_pmu_ops(gops);
348 gp10b_init_regops(gops); 413 gp10b_init_regops(gops);
349 gp10b_init_therm_ops(gops); 414 gp10b_init_therm_ops(gops);
350 gk20a_init_tsg_ops(gops);
351 gk20a_init_pramin_ops(gops); 415 gk20a_init_pramin_ops(gops);
352 416
353 g->name = "gp10b"; 417 g->name = "gp10b";