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authorSunny He <suhe@nvidia.com>2017-06-28 18:59:14 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-06 13:54:57 -0400
commit64076b4b214b45fe8367e467dd6796a9bcc058a4 (patch)
tree4d0fa3536fa188ec1f12f4349440b998cb608b77 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c
parent75d7d6826dea130d5eb5ac86f1ca54bd9b05fbe1 (diff)
gpu: nvgpu: Reorg misc HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I30d379bf52709c8382c9d7aa87f1672ca0f89c6f Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510386 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c146
1 files changed, 76 insertions, 70 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 505dc6d7..98ff55cc 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -52,74 +52,6 @@
52#include <nvgpu/hw/gp10b/hw_proj_gp10b.h> 52#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
53#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> 53#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
54 54
55static const struct gpu_ops gp10b_ops = {
56 .ltc = {
57 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
58 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
59 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
60 .init_cbc = gm20b_ltc_init_cbc,
61 .init_fs_state = gp10b_ltc_init_fs_state,
62 .init_comptags = gp10b_ltc_init_comptags,
63 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
64 .isr = gp10b_ltc_isr,
65 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
66 .flush = gm20b_flush_ltc,
67#ifdef CONFIG_DEBUG_FS
68 .sync_debugfs = gp10b_ltc_sync_debugfs,
69#endif
70 },
71 .clock_gating = {
72 .slcg_bus_load_gating_prod =
73 gp10b_slcg_bus_load_gating_prod,
74 .slcg_ce2_load_gating_prod =
75 gp10b_slcg_ce2_load_gating_prod,
76 .slcg_chiplet_load_gating_prod =
77 gp10b_slcg_chiplet_load_gating_prod,
78 .slcg_ctxsw_firmware_load_gating_prod =
79 gp10b_slcg_ctxsw_firmware_load_gating_prod,
80 .slcg_fb_load_gating_prod =
81 gp10b_slcg_fb_load_gating_prod,
82 .slcg_fifo_load_gating_prod =
83 gp10b_slcg_fifo_load_gating_prod,
84 .slcg_gr_load_gating_prod =
85 gr_gp10b_slcg_gr_load_gating_prod,
86 .slcg_ltc_load_gating_prod =
87 ltc_gp10b_slcg_ltc_load_gating_prod,
88 .slcg_perf_load_gating_prod =
89 gp10b_slcg_perf_load_gating_prod,
90 .slcg_priring_load_gating_prod =
91 gp10b_slcg_priring_load_gating_prod,
92 .slcg_pmu_load_gating_prod =
93 gp10b_slcg_pmu_load_gating_prod,
94 .slcg_therm_load_gating_prod =
95 gp10b_slcg_therm_load_gating_prod,
96 .slcg_xbar_load_gating_prod =
97 gp10b_slcg_xbar_load_gating_prod,
98 .blcg_bus_load_gating_prod =
99 gp10b_blcg_bus_load_gating_prod,
100 .blcg_ce_load_gating_prod =
101 gp10b_blcg_ce_load_gating_prod,
102 .blcg_ctxsw_firmware_load_gating_prod =
103 gp10b_blcg_ctxsw_firmware_load_gating_prod,
104 .blcg_fb_load_gating_prod =
105 gp10b_blcg_fb_load_gating_prod,
106 .blcg_fifo_load_gating_prod =
107 gp10b_blcg_fifo_load_gating_prod,
108 .blcg_gr_load_gating_prod =
109 gp10b_blcg_gr_load_gating_prod,
110 .blcg_ltc_load_gating_prod =
111 gp10b_blcg_ltc_load_gating_prod,
112 .blcg_pwr_csb_load_gating_prod =
113 gp10b_blcg_pwr_csb_load_gating_prod,
114 .blcg_pmu_load_gating_prod =
115 gp10b_blcg_pmu_load_gating_prod,
116 .blcg_xbar_load_gating_prod =
117 gp10b_blcg_xbar_load_gating_prod,
118 .pg_gr_load_gating_prod =
119 gr_gp10b_pg_gr_load_gating_prod,
120 }
121};
122
123static int gp10b_get_litter_value(struct gk20a *g, int value) 55static int gp10b_get_litter_value(struct gk20a *g, int value)
124{ 56{
125 int ret = EINVAL; 57 int ret = EINVAL;
@@ -209,6 +141,76 @@ static int gp10b_get_litter_value(struct gk20a *g, int value)
209 return ret; 141 return ret;
210} 142}
211 143
144static const struct gpu_ops gp10b_ops = {
145 .ltc = {
146 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
147 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
148 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
149 .init_cbc = gm20b_ltc_init_cbc,
150 .init_fs_state = gp10b_ltc_init_fs_state,
151 .init_comptags = gp10b_ltc_init_comptags,
152 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
153 .isr = gp10b_ltc_isr,
154 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
155 .flush = gm20b_flush_ltc,
156#ifdef CONFIG_DEBUG_FS
157 .sync_debugfs = gp10b_ltc_sync_debugfs,
158#endif
159 },
160 .clock_gating = {
161 .slcg_bus_load_gating_prod =
162 gp10b_slcg_bus_load_gating_prod,
163 .slcg_ce2_load_gating_prod =
164 gp10b_slcg_ce2_load_gating_prod,
165 .slcg_chiplet_load_gating_prod =
166 gp10b_slcg_chiplet_load_gating_prod,
167 .slcg_ctxsw_firmware_load_gating_prod =
168 gp10b_slcg_ctxsw_firmware_load_gating_prod,
169 .slcg_fb_load_gating_prod =
170 gp10b_slcg_fb_load_gating_prod,
171 .slcg_fifo_load_gating_prod =
172 gp10b_slcg_fifo_load_gating_prod,
173 .slcg_gr_load_gating_prod =
174 gr_gp10b_slcg_gr_load_gating_prod,
175 .slcg_ltc_load_gating_prod =
176 ltc_gp10b_slcg_ltc_load_gating_prod,
177 .slcg_perf_load_gating_prod =
178 gp10b_slcg_perf_load_gating_prod,
179 .slcg_priring_load_gating_prod =
180 gp10b_slcg_priring_load_gating_prod,
181 .slcg_pmu_load_gating_prod =
182 gp10b_slcg_pmu_load_gating_prod,
183 .slcg_therm_load_gating_prod =
184 gp10b_slcg_therm_load_gating_prod,
185 .slcg_xbar_load_gating_prod =
186 gp10b_slcg_xbar_load_gating_prod,
187 .blcg_bus_load_gating_prod =
188 gp10b_blcg_bus_load_gating_prod,
189 .blcg_ce_load_gating_prod =
190 gp10b_blcg_ce_load_gating_prod,
191 .blcg_ctxsw_firmware_load_gating_prod =
192 gp10b_blcg_ctxsw_firmware_load_gating_prod,
193 .blcg_fb_load_gating_prod =
194 gp10b_blcg_fb_load_gating_prod,
195 .blcg_fifo_load_gating_prod =
196 gp10b_blcg_fifo_load_gating_prod,
197 .blcg_gr_load_gating_prod =
198 gp10b_blcg_gr_load_gating_prod,
199 .blcg_ltc_load_gating_prod =
200 gp10b_blcg_ltc_load_gating_prod,
201 .blcg_pwr_csb_load_gating_prod =
202 gp10b_blcg_pwr_csb_load_gating_prod,
203 .blcg_pmu_load_gating_prod =
204 gp10b_blcg_pmu_load_gating_prod,
205 .blcg_xbar_load_gating_prod =
206 gp10b_blcg_xbar_load_gating_prod,
207 .pg_gr_load_gating_prod =
208 gr_gp10b_pg_gr_load_gating_prod,
209 },
210 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
211 .get_litter_value = gp10b_get_litter_value,
212};
213
212int gp10b_init_hal(struct gk20a *g) 214int gp10b_init_hal(struct gk20a *g)
213{ 215{
214 struct gpu_ops *gops = &g->ops; 216 struct gpu_ops *gops = &g->ops;
@@ -217,6 +219,12 @@ int gp10b_init_hal(struct gk20a *g)
217 219
218 gops->ltc = gp10b_ops.ltc; 220 gops->ltc = gp10b_ops.ltc;
219 gops->clock_gating = gp10b_ops.clock_gating; 221 gops->clock_gating = gp10b_ops.clock_gating;
222
223 /* Lone Functions */
224 gops->chip_init_gpu_characteristics =
225 gp10b_ops.chip_init_gpu_characteristics;
226 gops->get_litter_value = gp10b_ops.get_litter_value;
227
220 gops->pmupstate = false; 228 gops->pmupstate = false;
221#ifdef CONFIG_TEGRA_ACR 229#ifdef CONFIG_TEGRA_ACR
222 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 230 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
@@ -278,8 +286,6 @@ int gp10b_init_hal(struct gk20a *g)
278 gk20a_init_css_ops(gops); 286 gk20a_init_css_ops(gops);
279#endif 287#endif
280 g->name = "gp10b"; 288 g->name = "gp10b";
281 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
282 gops->get_litter_value = gp10b_get_litter_value;
283 289
284 c->twod_class = FERMI_TWOD_A; 290 c->twod_class = FERMI_TWOD_A;
285 c->threed_class = PASCAL_A; 291 c->threed_class = PASCAL_A;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 18:56:13 -0400