diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-17 19:11:34 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-24 12:34:43 -0400 |
commit | 4b5b67d6d83430d8d670660b1dfc9cf024d60d88 (patch) | |
tree | 541a421438fe849ee4b1ab9e6bdfa9e8b6ee4485 /drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |
parent | 82ba1277f3da7379ed6b8288c04bb91db008549c (diff) |
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Ie37638f442fd68aca8a7ade5f297118447bdc91e
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542989
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 129 |
1 files changed, 128 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 69a90031..d0f07a2b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "gk20a/mc_gk20a.h" | 27 | #include "gk20a/mc_gk20a.h" |
28 | #include "gk20a/fb_gk20a.h" | 28 | #include "gk20a/fb_gk20a.h" |
29 | #include "gk20a/pmu_gk20a.h" | 29 | #include "gk20a/pmu_gk20a.h" |
30 | #include "gk20a/gr_gk20a.h" | ||
30 | 31 | ||
31 | #include "gp10b/gr_gp10b.h" | 32 | #include "gp10b/gr_gp10b.h" |
32 | #include "gp10b/fecs_trace_gp10b.h" | 33 | #include "gp10b/fecs_trace_gp10b.h" |
@@ -179,6 +180,128 @@ static const struct gpu_ops gp10b_ops = { | |||
179 | .isr_stall = gp10b_ce_isr, | 180 | .isr_stall = gp10b_ce_isr, |
180 | .isr_nonstall = gp10b_ce_nonstall_isr, | 181 | .isr_nonstall = gp10b_ce_nonstall_isr, |
181 | }, | 182 | }, |
183 | .gr = { | ||
184 | .init_gpc_mmu = gr_gm20b_init_gpc_mmu, | ||
185 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, | ||
186 | .cb_size_default = gr_gp10b_cb_size_default, | ||
187 | .calc_global_ctx_buffer_size = | ||
188 | gr_gp10b_calc_global_ctx_buffer_size, | ||
189 | .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb, | ||
190 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
191 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
192 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
193 | .handle_sw_method = gr_gp10b_handle_sw_method, | ||
194 | .set_alpha_circular_buffer_size = | ||
195 | gr_gp10b_set_alpha_circular_buffer_size, | ||
196 | .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, | ||
197 | .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, | ||
198 | .is_valid_class = gr_gp10b_is_valid_class, | ||
199 | .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, | ||
200 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | ||
201 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | ||
202 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | ||
203 | .init_fs_state = gr_gp10b_init_fs_state, | ||
204 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | ||
205 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
206 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
207 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | ||
208 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | ||
209 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
210 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | ||
211 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | ||
212 | .get_zcull_info = gr_gk20a_get_zcull_info, | ||
213 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
214 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
215 | .detect_sm_arch = gr_gm20b_detect_sm_arch, | ||
216 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
217 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
218 | .zbc_set_table = gk20a_gr_zbc_set_table, | ||
219 | .zbc_query_table = gr_gk20a_query_zbc, | ||
220 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
221 | .add_zbc = gr_gk20a_add_zbc, | ||
222 | .pagepool_default_size = gr_gp10b_pagepool_default_size, | ||
223 | .init_ctx_state = gr_gp10b_init_ctx_state, | ||
224 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | ||
225 | .free_gr_ctx = gr_gp10b_free_gr_ctx, | ||
226 | .update_ctxsw_preemption_mode = | ||
227 | gr_gp10b_update_ctxsw_preemption_mode, | ||
228 | .dump_gr_regs = gr_gp10b_dump_gr_status_regs, | ||
229 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
230 | .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, | ||
231 | .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, | ||
232 | .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, | ||
233 | .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, | ||
234 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | ||
235 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | ||
236 | .wait_empty = gr_gp10b_wait_empty, | ||
237 | .init_cyclestats = gr_gp10b_init_cyclestats, | ||
238 | .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode, | ||
239 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
240 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | ||
241 | .get_access_map = gr_gp10b_get_access_map, | ||
242 | .handle_fecs_error = gr_gp10b_handle_fecs_error, | ||
243 | .handle_sm_exception = gr_gp10b_handle_sm_exception, | ||
244 | .handle_tex_exception = gr_gp10b_handle_tex_exception, | ||
245 | .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, | ||
246 | .enable_exceptions = gk20a_gr_enable_exceptions, | ||
247 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
248 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | ||
249 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | ||
250 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | ||
251 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
252 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | ||
253 | .suspend_contexts = gr_gp10b_suspend_contexts, | ||
254 | .resume_contexts = gr_gk20a_resume_contexts, | ||
255 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
256 | .fuse_override = gp10b_gr_fuse_override, | ||
257 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | ||
258 | .load_smid_config = gr_gp10b_load_smid_config, | ||
259 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | ||
260 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
261 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
262 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
263 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
264 | .setup_rop_mapping = gr_gk20a_setup_rop_mapping, | ||
265 | .program_zcull_mapping = gr_gk20a_program_zcull_mapping, | ||
266 | .commit_global_timeslice = gr_gk20a_commit_global_timeslice, | ||
267 | .commit_inst = gr_gk20a_commit_inst, | ||
268 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, | ||
269 | .write_pm_ptr = gr_gk20a_write_pm_ptr, | ||
270 | .init_elcg_mode = gr_gk20a_init_elcg_mode, | ||
271 | .load_tpc_mask = gr_gm20b_load_tpc_mask, | ||
272 | .inval_icache = gr_gk20a_inval_icache, | ||
273 | .trigger_suspend = gr_gk20a_trigger_suspend, | ||
274 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
275 | .resume_from_pause = gr_gk20a_resume_from_pause, | ||
276 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
277 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
278 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, | ||
279 | .sm_debugger_attached = gk20a_gr_sm_debugger_attached, | ||
280 | .suspend_single_sm = gk20a_gr_suspend_single_sm, | ||
281 | .suspend_all_sms = gk20a_gr_suspend_all_sms, | ||
282 | .resume_single_sm = gk20a_gr_resume_single_sm, | ||
283 | .resume_all_sms = gk20a_gr_resume_all_sms, | ||
284 | .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, | ||
285 | .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, | ||
286 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
287 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
288 | .lock_down_sm = gk20a_gr_lock_down_sm, | ||
289 | .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, | ||
290 | .clear_sm_hww = gm20b_gr_clear_sm_hww, | ||
291 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | ||
292 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | ||
293 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
294 | .set_boosted_ctx = gr_gp10b_set_boosted_ctx, | ||
295 | .set_preemption_mode = gr_gp10b_set_preemption_mode, | ||
296 | .set_czf_bypass = gr_gp10b_set_czf_bypass, | ||
297 | .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, | ||
298 | .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, | ||
299 | .init_preemption_state = gr_gp10b_init_preemption_state, | ||
300 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | ||
301 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
302 | .create_gr_sysfs = gr_gp10b_create_sysfs, | ||
303 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | ||
304 | }, | ||
182 | .fb = { | 305 | .fb = { |
183 | .reset = fb_gk20a_reset, | 306 | .reset = fb_gk20a_reset, |
184 | .init_hw = gk20a_fb_init_hw, | 307 | .init_hw = gk20a_fb_init_hw, |
@@ -474,6 +597,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
474 | 597 | ||
475 | gops->ltc = gp10b_ops.ltc; | 598 | gops->ltc = gp10b_ops.ltc; |
476 | gops->ce2 = gp10b_ops.ce2; | 599 | gops->ce2 = gp10b_ops.ce2; |
600 | gops->gr = gp10b_ops.gr; | ||
477 | gops->fb = gp10b_ops.fb; | 601 | gops->fb = gp10b_ops.fb; |
478 | gops->clock_gating = gp10b_ops.clock_gating; | 602 | gops->clock_gating = gp10b_ops.clock_gating; |
479 | gops->fifo = gp10b_ops.fifo; | 603 | gops->fifo = gp10b_ops.fifo; |
@@ -564,6 +688,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
564 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 688 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
565 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | 689 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; |
566 | gops->pmu.is_priv_load = gp10b_is_priv_load; | 690 | gops->pmu.is_priv_load = gp10b_is_priv_load; |
691 | |||
692 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
567 | } else { | 693 | } else { |
568 | /* Inherit from gk20a */ | 694 | /* Inherit from gk20a */ |
569 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, | 695 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, |
@@ -574,12 +700,13 @@ int gp10b_init_hal(struct gk20a *g) | |||
574 | gops->pmu.load_lsfalcon_ucode = NULL; | 700 | gops->pmu.load_lsfalcon_ucode = NULL; |
575 | gops->pmu.init_wpr_region = NULL; | 701 | gops->pmu.init_wpr_region = NULL; |
576 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | 702 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; |
703 | |||
704 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
577 | } | 705 | } |
578 | 706 | ||
579 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 707 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
580 | g->pmu_lsf_pmu_wpr_init_done = 0; | 708 | g->pmu_lsf_pmu_wpr_init_done = 0; |
581 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 709 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
582 | gp10b_init_gr(g); | ||
583 | 710 | ||
584 | gp10b_init_uncompressed_kind_map(); | 711 | gp10b_init_uncompressed_kind_map(); |
585 | gp10b_init_kind_attr(); | 712 | gp10b_init_kind_attr(); |