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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-09-18 14:06:09 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-19 20:45:28 -0400 |
commit | c4370d7deff6e3545157e06f51df2fef605a18cc (patch) | |
tree | def6acc583226bade58338ff1ac869636c6d88e0 /drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |
parent | c03ccd89c24572dcb65bdfc8d9ab5eb76da28c96 (diff) |
gpu: nvgpu: Initialize ctxsw header counters
Initialize following counters in context header
for all legacy chips:
ctxsw_prog_main_image_num_save_ops
ctxsw_prog_main_image_num_restore_ops
This was already present in the code but move to a function
gk20a_gr_init_ctxsw_hdr_data, so that it can be re-used across
chips.
Additionally initialize following preemption related counters
for gp10b onwards in context header:
ctxsw_prog_main_image_num_wfi_save_ops
ctxsw_prog_main_image_num_cta_save_ops
ctxsw_prog_main_image_num_gfxp_save_ops
ctxsw_prog_main_image_num_cilp_save_ops
Bug 1958308
Change-Id: I0e45ec718a8f9ddb951b52c92137051b4f6a8c60
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index ce1ca01f..4d7673da 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -133,6 +133,7 @@ int gr_gp10b_init_preemption_state(struct gk20a *g); | |||
133 | void gr_gp10b_set_preemption_buffer_va(struct gk20a *g, | 133 | void gr_gp10b_set_preemption_buffer_va(struct gk20a *g, |
134 | struct nvgpu_mem *mem, u64 gpu_va); | 134 | struct nvgpu_mem *mem, u64 gpu_va); |
135 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch); | 135 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch); |
136 | void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem); | ||
136 | 137 | ||
137 | struct gr_t18x { | 138 | struct gr_t18x { |
138 | struct { | 139 | struct { |